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# ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓ #
# ▓▓***-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*::::::::....................▓▓ #
# ▓▓*** Расшифровка машинных кодов процессора *::::::::::.$$$$$$$$$$$$$$$$$▓▓ #
# ▓▓***-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*::::::::::::................▓▓ #
# ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓ #
# #
# [ by Scorpio ] #
# #
# Когда-то давно работая еще на компьютере "ZX-Spectrum 48K" (Z80 = 8080) #
# и разбирая различные проги в Asm'е, мне часто помогал справочник, в #
# котором все машинные коды были расписаны по командам Asm'a. На компах #
# 8086, 80286, 80386, 80586, мне часто не хватало такого справочника, а #
# т.к. Z80 от х86 полностью отличается. Вот и решил написать свой, #
# представленный ниже справочник для процессоров от Intel 8086 до #
# Intel Pentium 4, Intel Xeon, включительно. #
# #
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Instruction Prefixes
Up to four prefixes of 1-byte each (optional)
+Lock and repeat prefixes.
- F0H-LOCK prefix.
- F2H-REPNE/REPNZ prefix (used only with string instructions).
- F3H-REP prefix (used only with string instructions).
- F3H-REPE/REPZ prefix (used only with string instructions).
+Segment override.
- 2EH-CS segment override prefix.
- 36H-SS segment override prefix.
- 3EH-DS segment override prefix.
- 26H-ES segment override prefix.
- 64H-FS segment override prefix.
- 65H-GS segment override prefix.
+Operand-size override, 66H
+Address-size override, 67H
Opcode
1 or 2 byte opcode
ModR/M
1 byte (if required)
bits xxx. .... R/M
bits ...x xx.. Reg/Opcode
bits .... ..xx MOD
SIB
1 byte (if required)
bits xxx. .... Base
bits ...x xx.. Index
bits .... ..xx Scale
Displacement
Address displacement of 1, 2, or 4 bytes or none
Immediate
Immediate data of 1, 2, or 4 bytes or none
OPCODE COLUMN
The "Opcode" column gives the complete object code produced for each form of the
instruction.
When possible, the codes are given as hexadecimal bytes, in the same order in which
they appear in memory. Definitions of entries other than hexadecimal bytes are as follows:
/digit A digit between 0 and 7 indicates that the ModR/M byte of the
instruction uses only the r/m (register or memory) operand. The reg
field contains the digit that provides an extension to the instruction's
opcode.
/r Indicates that the ModR/M byte of the instruction contains both a
register operand and an r/m operand.
cb, cw, cd, cp A 1-byte (cb), 2-byte (cw), 4-byte (cd), or 6-byte (cp) value
following the opcode that is used to specify a code offset and possibly
a new value for the code segment register.
ib, iw, id A 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand to the
instruction that follows the opcode, ModR/M bytes or scale-indexing
bytes. The opcode determines if the operand is a signed value. All words
and doublewords are given with the low-order byte first.
+rb, +rw, +rd A register code, from 0 through 7, added to the hexadecimal byte given
at the left of the plus sign to form a single opcode byte.
+i A number used in floating-point instructions when one of the operands is
ST(i) from the FPU register stack. The number i (which can range from 0
to 7) is added to the hexadecimal byte given at the left of the plus
sign to form a single opcode byte.
INSTRUCTION COLUMN
The "Instruction" column gives the syntax of the instruction statement as it would
appear in an ASM386 program. The following is a list of the symbols used to represent operands
in the instruction statements:
rel8 A relative address in the range from 128 bytes before the end of
the instruction to 127 bytes after the end of the instruction.
rel16 and rel32 A relative address within the same code segment as the
instruction assembled. The rel16 symbol applies to instructions
with an operand-size attribute of 16 bits; the rel32 symbol
applies to instructions with an operand-size attribute of 32
bits.
ptr16:16 and ptr16:32 A far pointer, typically in a code segment different from
that of the instruction. The notation 16:16 indicates that the
value of the pointer has two parts. The value to the left of the
colon is a 16-bit selector or value destined for the code
segment register. The value to the right corresponds to the
offset within the destination segment. The ptr16:16 symbol is
used when the instruction's operand-size attribute is 16 bits;
the ptr16:32 symbol is used when the operand-size attribute is
32 bits.
r8 One of the byte general-purpose registers AL, CL, DL, BL, AH,
CH, DH, or BH.
r16 One of the word general-purpose registers AX, CX, DX, BX, SP,
BP, SI, or DI.
r32 One of the doubleword general-purpose registers EAX, ECX, EDX,
EBX, ESP, EBP, ESI, or EDI.
imm8 An immediate byte value. The imm8 symbol is a signed number
between -128 and +127 inclusive. For instructions in which imm8
is combined with a word or doubleword operand, the immediate
value is sign-extended to form a word or doubleword. The upper
byte of the word is filled with the topmost bit of the immediate
value.
imm16 An immediate word value used for instructions whose operand-size
attribute is 16 bits. This is a number between -32,768
and +32,767 inclusive.
imm32 An immediate doubleword value used for instructions whose
operand-size attribute is 32 bits. It allows the use of a number
between +2,147,483,647 and -2,147,483,648 inclusive.
r/m8 A byte operand that is either the contents of a byte
general-purpose register (AL, BL, CL, DL, AH, BH, CH, and DH),
or a byte from memory.
r/m16 A word general-purpose register or memory operand used for
instructions whose operand-size attribute is 16 bits. The word
general-purpose registers are: AX, BX, CX, DX, SP, BP, SI, and
DI. The contents of memory are found at the address provided by
the effective address computation.
r/m32 A doubleword general-purpose register or memory operand used
for instructions whose operand-size attribute is 32 bits. The
doubleword general-purpose registers are: EAX, EBX, ECX, EDX,
ESP, EBP, ESI, and EDI. The contents of memory are found at the
address provided by the effective address computation.
m A 16- or 32-bit operand in memory.
m8 A byte operand in memory, usually expressed as a variable or
array name, but pointed to by the DS:(E)SI or ES:(E)DI
registers. This nomenclature is used only with the string
instructions and the XLAT instruction.
m16 A word operand in memory, usually expressed as a variable or
array name, but pointed to by the DS:(E)SI or ES:(E)DI
registers. This nomenclature is used only with the string
instructions.
m32 A doubleword operand in memory, usually expressed as a variable
or array name, but pointed to by the DS:(E)SI or ES:(E)DI
registers. This nomenclature is used only with the string
instructions.
m64 A memory quadword operand in memory. This nomenclature is used
only with the CMPXCHG8B instruction.
m128 A memory double quadword operand in memory. This nomenclature
is used only with the SSE and SSE2 instructions.
m16:16, m16:32 A memory operand containing a far pointer composed of two numbers.
The number to the left of the colon corresponds to the pointer's
segment selector. The number to the right corresponds to its
offset.
m16&32, m16&16, m32&32 A memory operand consisting of data item pairs whose sizes are
indicated on the left and the right side of the ampersand. All
memory addressing modes are allowed. The m16&16 and m32&32
operands are used by the BOUND instruction to provide an operand
containing an upper and lower bounds for array indices. The
m16&32 operand is used by LIDT and LGDT to provide a word with
which to load the limit field, and a doubleword with which to
load the base field of the corresponding GDTR and IDTR
registers.
moffs8, moffs16, moffs32 A simple memory variable (memory offset) of type byte, word, or
doubleword used by some variants of the MOV instruction. The
actual address is given by a simple offset relative to the
segment base. No ModR/M byte is used in the instruction. The
number shown with moffs indicates its size, which is determined
by the address-size attribute of the instruction.
Sreg A segment register. The segment register bit assignments are
ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5.
m32fp, m64fp, m80fp A single-precision, double-precision, and double
extended-precision (respectively) floating-point operand in
memory. These symbols designate floating-point values that are
used as operands for x87 FPU floating-point instructions.
m16int, m32int, m64int A word, doubleword, and quadword integer (respectively) operand
in memory. These symbols designate integers that are used as
operands for x87 FPU integer instructions.
ST or ST(0) The top element of the FPU register stack.
ST(i) The i-th element from the top of the FPU register stack. (i <0
through 7)
mm An MMX technology register. The 64-bit MMX technology registers
are: MM0 through MM7.
mm/m32 The low order 32 bits of an MMX technology register or a 32-bit
memory operand. The 64-bit MMX technology registers are: MM0
through MM7. The contents of memory are found at the address
provided by the effective address computation.
mm/m64 An MMX technology register or a 64-bit memory operand. The
64-bit MMX technology registers are: MM0 through MM7. The
contents of memory are found at the address provided by the
effective address computation.
xmm An XMM register. The 128-bit XMM registers are: XMM0 through
XMM7.
xmm/m32 An XMM register or a 32-bit memory operand. The 128-bit XMM
registers are XMM0 through XMM7. The contents of memory are
found at the address provided by the effective address
computation.
xmm/m64 An XMM register or a 64-bit memory operand. The 128-bit SIMD
floating-point registers are XMM0 through XMM7. The contents of
memory are found at the address provided by the effective
address computation.
xmm/m128 An XMM register or a 128-bit memory operand. The 128-bit XMM
registers are XMM0 through XMM7. The contents of memory are
found at the address provided by the effective address
computation.
Table 1. 16-Bit Addressing Forms with the ModR/M Byte
╔════════════════════════════════╦══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╗
║ r8(/r) ║ AL │ CL │ DL │ BL │ AH │ CH │ DH │ BH ║
║ r16(/r) ║ AX │ CX │ DX │ BX │ SP │ BP(1)│ SI │ DI ║
║ r32(/r) ║ EAX │ ECX │ EDX │ EBX │ ESP │ EBP │ ESI │ EDI ║
║ mm(/r) ║ MM0 │ MM1 │ MM2 │ MM3 │ MM4 │ MM5 │ MM6 │ MM7 ║
║ xmm(/r) ║ XMM0 │ XMM1 │ XMM2 │ XMM3 │ XMM4 │ XMM5 │ XMM6 │ XMM7 ║
║ /digit(Opcode) ║ 0 │ 1 │ 2 │ 3 │ 4 │ 5 │ 6 │ 7 ║
║ REG= ║ 000 │ 001 │ 010 │ 011 │ 100 │ 101 │ 110 │ 111 ║
╟────────────────────┬─────┬─────╫──────┴──────┴──────┴──────┴──────┴──────┴──────┴──────╢
║ Effective │ │ ║ ║
║ address │ Mod │ R/M ║ Value of ModR/M Byte (in Hexadecimal) ║
╠════════════════════╪═════╪═════╬══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╣
║ [BX+SI] │ 00 │ 000 ║ 00 │ 08 │ 10 │ 18 │ 20 │ 28 │ 30 │ 38 ║
║ [BX+DI] │ │ 001 ║ 01 │ 09 │ 11 │ 19 │ 21 │ 29 │ 31 │ 39 ║
║ [BP+SI] │ │ 010 ║ 02 │ 0A │ 12 │ 1A │ 22 │ 2A │ 32 │ 3A ║
║ [BP+DI] │ │ 011 ║ 03 │ 0B │ 13 │ 1B │ 23 │ 2B │ 33 │ 3B ║
║ [SI] │ │ 100 ║ 04 │ 0C │ 14 │ 1C │ 24 │ 2C │ 34 │ 3C ║
║ [DI] │ │ 101 ║ 05 │ 0D │ 15 │ 1D │ 25 │ 2D │ 35 │ 3D ║
║ disp16(2) │ │ 110 ║ 06 │ 0E │ 16 │ 1E │ 26 │ 2E │ 36 │ 3E ║
║ [BX] │ │ 111 ║ 07 │ 0F │ 17 │ 1F │ 27 │ 2F │ 37 │ 3F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [BX+SI]+disp8(3) │ 01 │ 000 ║ 40 │ 48 │ 50 │ 58 │ 60 │ 68 │ 70 │ 78 ║
║ [BX+DI]+disp8 │ │ 001 ║ 41 │ 49 │ 51 │ 59 │ 61 │ 69 │ 71 │ 79 ║
║ [BP+SI]+disp8 │ │ 010 ║ 42 │ 4A │ 52 │ 5A │ 62 │ 6A │ 72 │ 7A ║
║ [BP+DI]+disp8 │ │ 011 ║ 43 │ 4B │ 53 │ 5B │ 63 │ 6B │ 73 │ 7B ║
║ [SI]+disp8 │ │ 100 ║ 44 │ 4C │ 54 │ 5C │ 64 │ 6C │ 74 │ 7C ║
║ [DI]+disp8 │ │ 101 ║ 45 │ 4D │ 55 │ 5D │ 65 │ 6D │ 75 │ 7D ║
║ [BP]+disp8 │ │ 110 ║ 46 │ 4E │ 56 │ 5E │ 66 │ 6E │ 76 │ 7E ║
║ [BX]+disp8 │ │ 111 ║ 47 │ 4F │ 57 │ 5F │ 67 │ 6F │ 77 │ 7F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [BX+SI]+disp16 │ 10 │ 000 ║ 80 │ 88 │ 90 │ 98 │ A0 │ A8 │ B0 │ B8 ║
║ [BX+DI]+disp16 │ │ 001 ║ 81 │ 89 │ 91 │ 99 │ A1 │ A9 │ B1 │ B9 ║
║ [BP+SI]+disp16 │ │ 010 ║ 82 │ 8A │ 92 │ 9A │ A2 │ AA │ B2 │ BA ║
║ [BP+DI]+disp16 │ │ 011 ║ 83 │ 8B │ 93 │ 9B │ A3 │ AB │ B3 │ BB ║
║ [SI]+disp16 │ │ 100 ║ 84 │ 8C │ 94 │ 9C │ A4 │ AC │ B4 │ BC ║
║ [DI]+disp16 │ │ 101 ║ 85 │ 8D │ 95 │ 9D │ A5 │ AD │ B5 │ BD ║
║ [BP]+disp16 │ │ 110 ║ 86 │ 8E │ 96 │ 9E │ A6 │ AE │ B6 │ BE ║
║ [BX]+disp16 │ │ 111 ║ 87 │ 8F │ 97 │ 9F │ A7 │ AF │ B7 │ BF ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ EAX/AX/AL/MM0/XMM0 │ 11 │ 000 ║ C0 │ C8 │ D0 │ D8 │ E0 │ E8 │ F0 │ F8 ║
║ ECX/CX/CL/MM1/XMM1 │ │ 001 ║ C1 │ C9 │ D1 │ D9 │ E1 │ E9 │ F1 │ F9 ║
║ EDX/DX/DL/MM2/XMM2 │ │ 010 ║ C2 │ CA │ D2 │ DA │ E2 │ EA │ F2 │ FA ║
║ EBX/BX/BL/MM3/XMM3 │ │ 011 ║ C3 │ CB │ D3 │ DB │ E3 │ EB │ F3 │ FB ║
║ ESP/SP/AH/MM4/XMM4 │ │ 100 ║ C4 │ CC │ D4 │ DC │ E4 │ EC │ F4 │ FC ║
║ EBP/BP/CH/MM5/XMM5 │ │ 101 ║ C5 │ CD │ D5 │ DD │ E5 │ ED │ F5 │ FD ║
║ ESI/SI/DH/MM6/XMM6 │ │ 110 ║ C6 │ CE │ D6 │ DE │ E6 │ EE │ F6 │ FE ║
║ EDI/DI/BH/MM7/XMM7 │ │ 111 ║ C7 │ CF │ D7 │ DF │ E7 │ EF │ F7 │ FF ║
╚════════════════════╧═════╧═════╩══════╧══════╧══════╧══════╧══════╧══════╧══════╧══════╝
(1) The default segment register is SS for the effective addresses containing a BP index,
DS for other effec-tive addresses.
(2) The disp16 nomenclature denotes a 16-bit displacement that follows the ModR/M byte and
that is added to the index.
(3) The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and
that is sign-extended and added to the index.
Table 2. 32-Bit Addressing Forms with the ModR/M Byte
╔════════════════════════════════╦══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╗
║ r8(/r) ║ AL │ CL │ DL │ BL │ AH │ CH │ DH │ BH ║
║ r16(/r) ║ AX │ CX │ DX │ BX │ SP │ BP │ SI │ DI ║
║ r32(/r) ║ EAX │ ECX │ EDX │ EBX │ ESP │ EBP │ ESI │ EDI ║
║ mm(/r) ║ MM0 │ MM1 │ MM2 │ MM3 │ MM4 │ MM5 │ MM6 │ MM7 ║
║ xmm(/r) ║ XMM0 │ XMM1 │ XMM2 │ XMM3 │ XMM4 │ XMM5 │ XMM6 │ XMM7 ║
║ /digit(Opcode) ║ 0 │ 1 │ 2 │ 3 │ 4 │ 5 │ 6 │ 7 ║
║ REG= ║ 000 │ 001 │ 010 │ 011 │ 100 │ 101 │ 110 │ 111 ║
╟────────────────────┬─────┬─────╫──────┴──────┴──────┴──────┴──────┴──────┴──────┴──────╢
║ Effective │ │ ║ ║
║ address │ Mod │ R/M ║ Value of ModR/M Byte (in Hexadecimal) ║
╠════════════════════╪═════╪═════╬══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╣
║ [EAX] │ 00 │ 000 ║ 00 │ 08 │ 10 │ 18 │ 20 │ 28 │ 30 │ 38 ║
║ [ECX] │ │ 001 ║ 01 │ 09 │ 11 │ 19 │ 21 │ 29 │ 31 │ 39 ║
║ [EDX] │ │ 010 ║ 02 │ 0A │ 12 │ 1A │ 22 │ 2A │ 32 │ 3A ║
║ [EBX] │ │ 011 ║ 03 │ 0B │ 13 │ 1B │ 23 │ 2B │ 33 │ 3B ║
║ [--][--](1) │ │ 100 ║ 04 │ 0C │ 14 │ 1C │ 24 │ 2C │ 34 │ 3C ║
║ disp32(2) │ │ 101 ║ 05 │ 0D │ 15 │ 1D │ 25 │ 2D │ 35 │ 3D ║
║ [ESI] │ │ 110 ║ 06 │ 0E │ 16 │ 1E │ 26 │ 2E │ 36 │ 3E ║
║ [EDI] │ │ 111 ║ 07 │ 0F │ 17 │ 1F │ 27 │ 2F │ 37 │ 3F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [EAX]+disp8(3) │ 01 │ 000 ║ 40 │ 48 │ 50 │ 58 │ 60 │ 68 │ 70 │ 78 ║
║ [ECX]+disp8 │ │ 001 ║ 41 │ 49 │ 51 │ 59 │ 61 │ 69 │ 71 │ 79 ║
║ [EDX]+disp8 │ │ 010 ║ 42 │ 4A │ 52 │ 5A │ 62 │ 6A │ 72 │ 7A ║
║ [EBX]+disp8 │ │ 011 ║ 43 │ 4B │ 53 │ 5B │ 63 │ 6B │ 73 │ 7B ║
║ [--][--]+disp8 │ │ 100 ║ 44 │ 4C │ 54 │ 5C │ 64 │ 6C │ 74 │ 7C ║
║ [EBP]+disp8 │ │ 101 ║ 45 │ 4D │ 55 │ 5D │ 65 │ 6D │ 75 │ 7D ║
║ [ESI]+disp8 │ │ 110 ║ 46 │ 4E │ 56 │ 5E │ 66 │ 6E │ 76 │ 7E ║
║ [EDI]+disp8 │ │ 111 ║ 47 │ 4F │ 57 │ 5F │ 67 │ 6F │ 77 │ 7F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [EAX]+disp32 │ 10 │ 000 ║ 80 │ 88 │ 90 │ 98 │ A0 │ A8 │ B0 │ B8 ║
║ [ECX]+disp32 │ │ 001 ║ 81 │ 89 │ 91 │ 99 │ A1 │ A9 │ B1 │ B9 ║
║ [EDX]+disp32 │ │ 010 ║ 82 │ 8A │ 92 │ 9A │ A2 │ AA │ B2 │ BA ║
║ [EBX]+disp32 │ │ 011 ║ 83 │ 8B │ 93 │ 9B │ A3 │ AB │ B3 │ BB ║
║ [--][--]+disp32 │ │ 100 ║ 84 │ 8C │ 94 │ 9C │ A4 │ AC │ B4 │ BC ║
║ [EBP]+disp32 │ │ 101 ║ 85 │ 8D │ 95 │ 9D │ A5 │ AD │ B5 │ BD ║
║ [ESI]+disp32 │ │ 110 ║ 86 │ 8E │ 96 │ 9E │ A6 │ AE │ B6 │ BE ║
║ [EDI]+disp32 │ │ 111 ║ 87 │ 8F │ 97 │ 9F │ A7 │ AF │ B7 │ BF ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ EAX/AX/AL/MM0/XMM0 │ 11 │ 000 ║ C0 │ C8 │ D0 │ D8 │ E0 │ E8 │ F0 │ F8 ║
║ ECX/CX/CL/MM1/XMM1 │ │ 001 ║ C1 │ C9 │ D1 │ D9 │ E1 │ E9 │ F1 │ F9 ║
║ EDX/DX/DL/MM2/XMM2 │ │ 010 ║ C2 │ CA │ D2 │ DA │ E2 │ EA │ F2 │ FA ║
║ EBX/BX/BL/MM3/XMM3 │ │ 011 ║ C3 │ CB │ D3 │ DB │ E3 │ EB │ F3 │ FB ║
║ ESP/SP/AH/MM4/XMM4 │ │ 100 ║ C4 │ CC │ D4 │ DC │ E4 │ EC │ F4 │ FC ║
║ EBP/BP/CH/MM5/XMM5 │ │ 101 ║ C5 │ CD │ D5 │ DD │ E5 │ ED │ F5 │ FD ║
║ ESI/SI/DH/MM6/XMM6 │ │ 110 ║ C6 │ CE │ D6 │ DE │ E6 │ EE │ F6 │ FE ║
║ EDI/DI/BH/MM7/XMM7 │ │ 111 ║ C7 │ CF │ D7 │ DF │ E7 │ EF │ F7 │ FF ║
╚════════════════════╧═════╧═════╩══════╧══════╧══════╧══════╧══════╧══════╧══════╧══════╝
(1) The [--][--] nomenclature means a SIB follows the ModR/M byte.
(2) The disp32 nomenclature denotes a 32-bit displacement that follows ModR/M byte (or the
SIB byte if one is present) and that is added to the index.
(3) The disp8 nomenclature denotes an 8-bit displacement that follows ModR/M byte (or the
SIB byte if one is present) and that is sign-extended and added to the index.
Table 3. 32-Bit Addressing Forms with the SIB Byte
╔════════════════════════════════╦══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╗
║ r32(/r) ║ EAX │ ECX │ EDX │ EBX │ ESP │ [*] │ ESI │ EDI ║
║ Base = ║ 0 │ 1 │ 2 │ 3 │ 4 │ 5 │ 6 │ 7 ║
║ Base = ║ 000 │ 001 │ 010 │ 011 │ 100 │ 101 │ 110 │ 111 ║
╟────────────────────┬─────┬─────╫──────┴──────┴──────┴──────┴──────┴──────┴──────┴──────╢
║ Scaled Index │ SS │Index║ Value of SIB Byte (in Hexadecimal) ║
╠════════════════════╪═════╪═════╬══════╤══════╤══════╤══════╤══════╤══════╤══════╤══════╣
║ [EAX] │ 00 │ 000 ║ 00 │ 08 │ 10 │ 18 │ 20 │ 28 │ 30 │ 38 ║
║ [ECX] │ │ 001 ║ 01 │ 09 │ 11 │ 19 │ 21 │ 29 │ 31 │ 39 ║
║ [EDX] │ │ 010 ║ 02 │ 0A │ 12 │ 1A │ 22 │ 2A │ 32 │ 3A ║
║ [EBX] │ │ 011 ║ 03 │ 0B │ 13 │ 1B │ 23 │ 2B │ 33 │ 3B ║
║ none │ │ 100 ║ 04 │ 0C │ 14 │ 1C │ 24 │ 2C │ 34 │ 3C ║
║ [EBP] │ │ 101 ║ 05 │ 0D │ 15 │ 1D │ 25 │ 2D │ 35 │ 3D ║
║ [ESI] │ │ 110 ║ 06 │ 0E │ 16 │ 1E │ 26 │ 2E │ 36 │ 3E ║
║ [EDI] │ │ 111 ║ 07 │ 0F │ 17 │ 1F │ 27 │ 2F │ 37 │ 3F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [EAX*2] │ 01 │ 000 ║ 40 │ 48 │ 50 │ 58 │ 60 │ 68 │ 70 │ 78 ║
║ [ECX*2] │ │ 001 ║ 41 │ 49 │ 51 │ 59 │ 61 │ 69 │ 71 │ 79 ║
║ [EDX*2] │ │ 010 ║ 42 │ 4A │ 52 │ 5A │ 62 │ 6A │ 72 │ 7A ║
║ [EBX*2] │ │ 011 ║ 43 │ 4B │ 53 │ 5B │ 63 │ 6B │ 73 │ 7B ║
║ none │ │ 100 ║ 44 │ 4C │ 54 │ 5C │ 64 │ 6C │ 74 │ 7C ║
║ [EBP*2] │ │ 101 ║ 45 │ 4D │ 55 │ 5D │ 65 │ 6D │ 75 │ 7D ║
║ [ESI*2] │ │ 110 ║ 46 │ 4E │ 56 │ 5E │ 66 │ 6E │ 76 │ 7E ║
║ [EDI*2] │ │ 111 ║ 47 │ 4F │ 57 │ 5F │ 67 │ 6F │ 77 │ 7F ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [EAX*4] │ 10 │ 000 ║ 80 │ 88 │ 90 │ 98 │ A0 │ A8 │ B0 │ B8 ║
║ [ECX*4] │ │ 001 ║ 81 │ 89 │ 91 │ 99 │ A1 │ A9 │ B1 │ B9 ║
║ [EDX*4] │ │ 010 ║ 82 │ 8A │ 92 │ 9A │ A2 │ AA │ B2 │ BA ║
║ [EBX*4] │ │ 011 ║ 83 │ 8B │ 93 │ 9B │ A3 │ AB │ B3 │ BB ║
║ none │ │ 100 ║ 84 │ 8C │ 94 │ 9C │ A4 │ AC │ B4 │ BC ║
║ [EBP*4] │ │ 101 ║ 85 │ 8D │ 95 │ 9D │ A5 │ AD │ B5 │ BD ║
║ [ESI*4] │ │ 110 ║ 86 │ 8E │ 96 │ 9E │ A6 │ AE │ B6 │ BE ║
║ [EDI*4] │ │ 111 ║ 87 │ 8F │ 97 │ 9F │ A7 │ AF │ B7 │ BF ║
╟────────────────────┼─────┼─────╫──────┼──────┼──────┼──────┼──────┼──────┼──────┼──────║
║ [EAX*8] │ 11 │ 000 ║ C0 │ C8 │ D0 │ D8 │ E0 │ E8 │ F0 │ F8 ║
║ [ECX*8] │ │ 001 ║ C1 │ C9 │ D1 │ D9 │ E1 │ E9 │ F1 │ F9 ║
║ [EDX*8] │ │ 010 ║ C2 │ CA │ D2 │ DA │ E2 │ EA │ F2 │ FA ║
║ [EBX*8] │ │ 011 ║ C3 │ CB │ D3 │ DB │ E3 │ EB │ F3 │ FB ║
║ none │ │ 100 ║ C4 │ CC │ D4 │ DC │ E4 │ EC │ F4 │ FC ║
║ [EBP*8] │ │ 101 ║ C5 │ CD │ D5 │ DD │ E5 │ ED │ F5 │ FD ║
║ [ESI*8] │ │ 110 ║ C6 │ CE │ D6 │ DE │ E6 │ EE │ F6 │ FE ║
║ [EDI*8] │ │ 111 ║ C7 │ CF │ D7 │ DF │ E7 │ EF │ F7 │ FF ║
╚════════════════════╧═════╧═════╩══════╧══════╧══════╧══════╧══════╧══════╧══════╧══════╝
The [*] nomenclature means a disp32 with no base if the MOD is 00b. Otherwise, [*] means
disp8 or disp32 + [EBP]. This provides the following address modes:
MOD bits Effective Address
00 [scaled index] + disp32
01 [scaled index] + disp8 + [EBP]
10 [scaled index] + disp32 + [EBP]
Table 4. Register Encodings Associated with
the +rb, +rw, and +rd Nomenclature
┌────────┬────────┬─────────┐
│ rb │ rw │ rd │
│ AL = 0 │ AX = 0 │ EAX = 0 │
│ CL = 1 │ CX = 1 │ ECX = 1 │
│ DL = 2 │ DX = 2 │ EDX = 2 │
│ BL = 3 │ BX = 3 │ EBX = 3 │
├────────┼────────┼─────────┤
│ rb │ rw │ rd │
│ AH = 4 │ SP = 4 │ ESP = 4 │
│ CH = 5 │ BP = 5 │ EBP = 5 │
│ DH = 6 │ SI = 6 │ ESI = 6 │
│ BH = 7 │ DI = 7 │ EDI = 7 │
└────────┴────────┴─────────┘
Opcode Instruction Description
00 /r ADD r/m8,r8 Add r8 to r/m8
01 /r ADD r/m16,r16 Add r16 to r/m16
01 /r ADD r/m32,r32 Add r32 to r/m32
02 /r ADD r8,r/m8 Add r/m8 to r8
03 /r ADD r16,r/m16 Add r/m16 to r16
03 /r ADD r32,r/m32 Add r/m32 to r32
04 ib ADD AL, imm8 Add imm8 to AL
05 iw ADD AX, imm16 Add imm16 to AX
05 id ADD EAX, imm32 Add imm32 to EAX
06 PUSH ES Push ES
07 POP ES Pop top of stack into ES; increment stack pointer
08 /r OR r/m8,r8 r/m8 OR r8
09 /r OR r/m16,r16 r/m16 OR r16
09 /r OR r/m32,r32 r/m32 OR r32
0A /r OR r8,r/m8 r8 OR r/m8
0B /r OR r16,r/m16 r16 OR r/m16
0B /r OR r32,r/m32 r32 OR r/m32
0C ib OR AL, imm8 AL OR imm8
0D iw OR AX, imm16 AX OR imm16
0D id OR EAX, imm32 EAX OR imm32
0E PUSH CS Push CS
0F 00 /0 SLDT r/m16 Stores segment selector from LDTR in r/m16
0F 00 /0 SLDT r/m32 Store segment selector from LDTR in low-order 16 bits of r/m32
0F 00 /1 STR r/m16 Stores segment selector from TR in r/m16
0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR
0F 00 /3 LTR r/m16 Load r/m16 into task register
0F 00 /4 VERR r/m16 Set ZF=1 if segment specified with r/m16 can be read
0F 00 /5 VERW r/m16 Set ZF=1 if segment specified with r/m16 can be written
0F 01 /0 SGDT m Store GDTR to m
0F 01 /1 SIDT m Store IDTR to m
0F 01 /2 LGDT m16&32 Load m into GDTR
0F 01 /3 LIDT m16&32 Load m into IDTR
0F 01 /4 SMSW r/m16 Store machine status word to r/m16
0F 01 /4 SMSW r32/m16 Store machine status word in low-order 16 bits of r32/m16; high-order 16 bits of r32 are undefined
0F 01 /6 LMSW r/m16 Loads r/m16 in machine status word of CR0
0F 01 /7 INVLPG m Invalidate TLB Entry for page that contains m
0F 02 /r LAR r16,r/m16 r16 <- r/m16 masked by FF00H
0F 02 /r LAR r32,r/m32 r32 <- r/m32 masked by 00FxFF00H
0F 03 /r LSL r16,r/m16 Load: r16 <- segment limit, selector r/m16
0F 03 /r LSL r32,r/m32 Load: r32 <- segment limit, selector r/m32)
0F 06 CLTS Clears TS flag in CR0
0F 08 INVD Flush internal caches; initiate flushing of external caches.
0F 09 WBINVD Write back and flush Internal caches; initiate writing-back and flushing of external caches.
0F 0B UD2 Raise invalid opcode exception
0F 10 /r MOVUPS xmm1, xmm2/m128 Move packed single-precision floating-point values from xmm2/m128 to xmm1.
0F 11 /r MOVUPS xmm2/m128, xmm1 Move packed single-precision floating-point values from xmm1 to xmm2/m128.
0F 12 /r MOVHLPS xmm1, xmm2 Move two packed single-precision floating-point values from high quadword of xmm2 to low quadword of xmm1.
0F 12 /r MOVLPS xmm, m64 Move two packed single-precision floating-point values from m64 to low quadword of xmm.
0F 13 /r MOVLPS m64, xmm Move two packed single-precision floating-point values from low quadword of xmm to m64.
0F 14 /r UNPCKLPS xmm1, xmm2/m128 Unpacks and Interleaves single-precision floating-point values from low quadwords of xmm1 and xmm2/mem into xmm1.
0F 15 /r UNPCKHPS xmm1, xmm2/m128 Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm1 and xmm2/mem into xmm1.
0F 16 /r MOVHPS xmm, m64 Move two packed single-precision floating-point values from m64 to high quadword of xmm.
0F 16 /r MOVLHPS xmm1, xmm2 Move two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1.
0F 17 /r MOVHPS m64, xmm Move two packed single-precision floating-point values from high quadword of xmm to m64.
0F 18 /0 PREFETCHNTA m8 Move data from m8 closer to the processor using NTA hint.
0F 18 /1 PREFETCHT0 m8 Move data from m8 closer to the processor using T0 hint.
0F 18 /2 PREFETCHT1 m8 Move data from m8 closer to the processor using T1 hint.
0F 18 /3 PREFETCHT2 m8 Move data from m8 closer to the processor using T2 hint.
0F 20 /r MOV r32,CR0 Move CR0 to r32
0F 20 /r MOV r32,CR2 Move CR2 to r32
0F 20 /r MOV r32,CR3 Move CR3 to r32
0F 20 /r MOV r32,CR4 Move CR4 to r32
0F 21 /r MOV r32, DR0-DR7 Move debug register to r32
0F 22 /r MOV CR0, r32 Move r32 to CR0
0F 22 /r MOV CR2, r32 Move r32 to CR2
0F 22 /r MOV CR3, r32 Move r32 to CR3
0F 22 /r MOV CR4, r32 Move r32 to CR4
0F 23 /r MOV DR0-DR7, r32 Move r32 to debug register
0F 28 /r MOVAPS xmm1, xmm2/m128 Move packed single-precision floating-point values from xmm2/m128 to xmm1.
0F 29 /r MOVAPS xmm2/m128, xmm1 Move packed single-precision floating-point values from xmm1 to xmm2/m128.
0F 2A /r CVTPI2PS xmm, mm/m64 Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm.
0F 2B /r MOVNTPS m128, xmm Move packed single-precision floating-point values from xmm to m128 using non-temporal hint.
0F 2C /r CVTTPS2PI mm, xmm/m64 Convert two single-precision floating-point values from xmm/m64 to two signed doubleword signed integers in mm using truncation.
0F 2D /r CVTPS2PI mm, xmm/m64 Convert two packed single-precision floating-point values from xmm/m64 to two packed signed doubleword integers in mm.
0F 2E /r UCOMISS xmm1, xmm2/m32 Compare lower single-precision floating-point value in xmm1 register with lower single-precision floating-point value in xmm2/mem and set the status flags accordingly.
0F 2F /r COMISS xmm1, xmm2/m32 Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.
0F 30 WRMSR Write the value in EDX:EAX to MSR specified by ECX
0F 31 RDTSC Read time-stamp counter into EDX:EAX
0F 32 RDMSR Load MSR specified by ECX into EDX:EAX
0F 33 RDPMC Read performance-monitoring counter specified by ECX into EDX:EAX
0F 34 SYSENTER Fast call to privilege level 0 system procedures
0F 35 SYSEXIT Fast return to privilege level 3 user code.
0F 40 /r CMOVO r16, r/m16 Move if overflow (OF=0)
0F 40 /r CMOVO r32, r/m32 Move if overflow (OF=0)
0F 41 /r CMOVNO r16, r/m16 Move if not overflow (OF=0)
0F 41 /r CMOVNO r32, r/m32 Move if not overflow (OF=0)
0F 42 /r CMOVB r16, r/m16 Move if below (CF=1)
0F 42 /r CMOVB r32, r/m32 Move if below (CF=1)
0F 42 /r CMOVC r16, r/m16 Move if carry (CF=1)
0F 42 /r CMOVC r32, r/m32 Move if carry (CF=1)
0F 42 /r CMOVNAE r16, r/m16 Move if not above or equal (CF=1)
0F 42 /r CMOVNAE r32, r/m32 Move if not above or equal (CF=1)
0F 43 /r CMOVAE r16, r/m16 Move if above or equal (CF=0)
0F 43 /r CMOVAE r32, r/m32 Move if above or equal (CF=0)
0F 43 /r CMOVNB r16, r/m16 Move if not below (CF=0)
0F 43 /r CMOVNB r32, r/m32 Move if not below (CF=0)
0F 43 /r CMOVNC r16, r/m16 Move if not carry (CF=0)
0F 43 /r CMOVNC r32, r/m32 Move if not carry (CF=0)
0F 44 /r CMOVE r16, r/m16 Move if equal (ZF=1)
0F 44 /r CMOVE r32, r/m32 Move if equal (ZF=1)
0F 44 /r CMOVZ r16, r/m16 Move if zero (ZF=1)
0F 44 /r CMOVZ r32, r/m32 Move if zero (ZF=1)
0F 45 /r CMOVNE r16, r/m16 Move if not equal (ZF=0)
0F 45 /r CMOVNE r32, r/m32 Move if not equal (ZF=0)
0F 45 /r CMOVNZ r16, r/m16 Move if not zero (ZF=0)
0F 45 /r CMOVNZ r32, r/m32 Move if not zero (ZF=0)
0F 46 /r CMOVBE r16, r/m16 Move if below or equal (CF=1 or ZF=1)
0F 46 /r CMOVBE r32, r/m32 Move if below or equal (CF=1 or ZF=1)
0F 46 /r CMOVNA r16, r/m16 Move if not above (CF=1 or ZF=1)
0F 46 /r CMOVNA r32, r/m32 Move if not above (CF=1 or ZF=1)
0F 47 /r CMOVA r16, r/m16 Move if above (CF=0 and ZF=0)
0F 47 /r CMOVA r32, r/m32 Move if above (CF=0 and ZF=0)
0F 47 /r CMOVNBE r16, r/m16 Move if not below or equal (CF=0 and ZF=0)
0F 47 /r CMOVNBE r32, r/m32 Move if not below or equal (CF=0 and ZF=0)
0F 48 /r CMOVS r16, r/m16 Move if sign (SF=1)
0F 48 /r CMOVS r32, r/m32 Move if sign (SF=1)
0F 49 /r CMOVNS r16, r/m16 Move if not sign (SF=0)
0F 49 /r CMOVNS r32, r/m32 Move if not sign (SF=0)
0F 4A /r CMOVP r16, r/m16 Move if parity (PF=1)
0F 4A /r CMOVP r32, r/m32 Move if parity (PF=1)
0F 4A /r CMOVPE r16, r/m16 Move if parity even (PF=1)
0F 4A /r CMOVPE r32, r/m32 Move if parity even (PF=1)
0F 4B /r CMOVNP r16, r/m16 Move if not parity (PF=0)
0F 4B /r CMOVNP r32, r/m32 Move if not parity (PF=0)
0F 4B /r CMOVPO r16, r/m16 Move if parity odd (PF=0)
0F 4B /r CMOVPO r32, r/m32 Move if parity odd (PF=0)
0F 4C /r CMOVL r16, r/m16 Move if less (SF<>OF)
0F 4C /r CMOVL r32, r/m32 Move if less (SF<>OF)
0F 4C /r CMOVNGE r16, r/m16 Move if not greater or equal (SF<>OF)
0F 4C /r CMOVNGE r32, r/m32 Move if not greater or equal (SF<>OF)
0F 4D /r CMOVGE r16, r/m16 Move if greater or equal (SF=OF)
0F 4D /r CMOVGE r32, r/m32 Move if greater or equal (SF=OF)
0F 4D /r CMOVNL r16, r/m16 Move if not less (SF=OF)
0F 4D /r CMOVNL r32, r/m32 Move if not less (SF=OF)
0F 4E /r CMOVLE r16, r/m16 Move if less or equal (ZF=1 or SF<>OF)
0F 4E /r CMOVLE r32, r/m32 Move if less or equal (ZF=1 or SF<>OF)
0F 4E /r CMOVNG r16, r/m16 Move if not greater (ZF=1 or SF<>OF)
0F 4E /r CMOVNG r32, r/m32 Move if not greater (ZF=1 or SF<>OF)
0F 4F /r CMOVG r16, r/m16 Move if greater (ZF=0 and SF=OF)
0F 4F /r CMOVG r32, r/m32 Move if greater (ZF=0 and SF=OF)
0F 4F /r CMOVNLE r16, r/m16 Move if not less or equal (ZF=0 and SF=OF)
0F 4F /r CMOVNLE r32, r/m32 Move if not less or equal (ZF=0 and SF=OF)
0F 50 /r MOVMSKPS r32, xmm Extract 4-bit sign mask of from xmm and store in r32.
0F 51 /r SQRTPS xmm1, xmm2/m128 Computes square roots of the packed single-precision floating-point values in xmm2/m128 and stores the results in xmm1.
0F 52 /r RSQRTPS xmm1, xmm2/m128 Computes the approximate reciprocals of the square roots of the packed single-precision floating-point values in xmm2/m128 and stores the results in xmm1.
0F 53 /r RCPPS xmm1, xmm2/m128 Computes the approximate reciprocals of the packed single-precision floating-point values in xmm2/m128 and stores the results in xmm1.
0F 54 /r ANDPS xmm1, xmm2/m128 Bitwise logical AND of xmm2/m128 and xmm1.
0F 55 /r ANDNPS xmm1, xmm2/m128 Bitwise logical AND NOT of xmm2/m128 and xmm1.
0F 56 /r ORPS xmm1, xmm2/m128 Bitwise OR of xmm2/m128 and xmm1
0F 57 /r XORPS xmm1, xmm2/m128 Bitwise exclusive-OR of xmm2/m128 and xmm1.
0F 58 /r ADDPS xmm1, xmm2/m128 Add packed single-precision floating-point values from xmm2/m128 to xmm1.
0F 59 /r MULPS xmm1, xmm2/m128 Multiply packed single-precision floating-point values in xmm2/mem by xmm1.
0F 5A /r CVTPS2PD xmm1, xmm2/m64 Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1.
0F 5B /r CVTDQ2PS xmm1, xmm2/m128 Convert four packed signed doubleword integers from xmm2/m128 to four packed single-precision floating-point values in xmm1.
0F 5C /r SUBPS xmm1 xmm2/m128 Subtract packed single-precision floating-point values in xmm2/mem from xmm1.
0F 5D /r MINPS xmm1, xmm2/m128 Return the minimum single-precision floating-point values between xmm2/m128 and xmm1.
0F 5E /r DIVPS xmm1, xmm2/m128 Divide packed single-precision floating-point values in xmm1 by packed single-precision floating-point values xmm2/m128.
0F 5F /r MAXPS xmm1, xmm2/m128 Return the maximum single-precision floating-point values between xmm2/m128 and xmm1.
0F 60 /r PUNPCKLBW mm, mm/m32 Interleave low-order bytes from mm and mm/m64 into mm.
0F 61 /r PUNPCKLWD mm, mm/m32 Interleave low-order words from mm and mm/m64 into mm.
0F 62 /r PUNPCKLDQ mm, mm/m32 Interleave low-order doublewords from mm and mm/m64 into mm.
0F 63 /r PACKSSWB mm, mm/m64 Packs and saturate pack 4 signed words from mm and 4 signed words from mm/m64 into 8 signed bytes in mm.
0F 63 /r PACKSSWB mm1, mm2/m64 Converts 4 packed signed word integers from mm1 and from mm2/m64 into 8 packed signed byte integers in mm1 using signed saturation.
0F 64 /r PCMPGTB mm, mm/m64 Compare packed bytes in mm with packed bytes in mm/m64 for greater value.
0F 65 /r PCMPGTW mm, mm/m64 Compare packed words in mm with packed words in mm/m64 for greater value.
0F 66 /r PCMPGTD mm, mm/m64 Compare packed doublewords in mm with packed doublewords in mm/m64 for greater value.
0F 67 /r PACKUSWB mm, mm/m64 Converts 4 signed word integers from mm and 4 signed word integers from mm/m64 into 8 unsigned byte integers in mm using unsigned saturation.
0F 68 /r PUNPCKHBW mm, mm/m64 Interleave high-order bytes from mm and mm/m64 into mm.
0F 69 /r PUNPCKHWD mm, mm/m64 Interleave high-order words from mm and mm/m64 into mm.
0F 6A /r PUNPCKHDQ mm, mm/m64 Interleave high-order doublewords from mm and mm/m64 into mm.
0F 6B /r PACKSSDW mm, mm/m64 Pack and saturate 2 signed doublewords from mm and 2 signed doublewords from mm/m64 into 4 signed words in mm.
0F 6B /r PACKSSDW mm1, mm2/m64 Converts 2 packed signed doubleword integers from mm1 and from mm2/m64 into 4 packed signed word integers in mm1 using signed saturation.
0F 6E /r MOVD mm, r/m32 Move doubleword from r/m32 to mm.
0F 6F /r MOVQ mm, mm/m64 Move quadword from mm/m64 to mm.
0F 70 /r ib PSHUFW mm1, mm2/m64, imm8 Shuffle the words in mm2/m64 based on the encoding in imm8 and store the result in mm1.
0F 71 /2 ib PSRLW mm, imm8 Shift words in mm right by imm8.
0F 71 /4 ib PSRAW mm, imm8 Shift words in mm right by imm8 while shifting in sign bits
0F 71 /6 ib PSLLW mm, imm8 Shift words in mm left by imm8, while shifting in zeros.
0F 72 /2 ib PSRLD mm, imm8 Shift doublewords in mm right by imm8.
0F 72 /4 ib PSRAD mm, imm8 Shift doublewords in mm right by imm8 while shifting in sign bits.
0F 72 /6 ib PSLLD mm, imm8 Shift doublewords in mm by imm8, while shifting in zeros.
0F 73 /2 ib PSRLQ mm, imm8 Shift mm right by imm8 while shifting in zeros.
0F 73 /6 ib PSLLQ mm, imm8 Shift mm left by Imm8, while shifting in zeros.
0F 74 /r PCMPEQB mm, mm/m64 Compare packed bytes in mm/m64 with packed bytes in mm for equality.
0F 75 /r PCMPEQW mm, mm/m64 Compare packed words in mm/m64 with packed words in mm for equality.
0F 76 /r PCMPEQD mm, mm/m64 Compare packed doublewords in mm/m64 with packed doublewords in mm for equality.
0F 77 EMMS Set the FP tag word to empty.
0F 7E /r MOVD r/m32, mm Move doubleword from mm to r/m32.
0F 7F /r MOVQ mm/m64, mm Move quadword from mm to mm/m64.
0F 80 cw/cd JO rel16/32 Jump near if overflow (OF=1)
0F 81 cw/cd JNO rel16/32 Jump near if not overflow (OF=0)
0F 82 cw/cd JB rel16/32 Jump near if below (CF=1)
0F 82 cw/cd JC rel16/32 Jump near if carry (CF=1)
0F 82 cw/cd JNAE rel16/32 Jump near if not above or equal (CF=1)
0F 83 cw/cd JAE rel16/32 Jump near if above or equal (CF=0)
0F 83 cw/cd JNB rel16/32 Jump near if not below (CF=0)
0F 83 cw/cd JNC rel16/32 Jump near if not carry (CF=0)
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)
0F 85 cw/cd JNE rel16/32 Jump near if not equal (ZF=0)
0F 85 cw/cd JNZ rel16/32 Jump near if not zero (ZF=0)
0F 86 cw/cd JBE rel16/32 Jump near if below or equal (CF=1 or ZF=1)
0F 86 cw/cd JNA rel16/32 Jump near if not above (CF=1 or ZF=1)
0F 87 cw/cd JA rel16/32 Jump near if above (CF=0 and ZF=0)
0F 87 cw/cd JNBE rel16/32 Jump near if not below or equal (CF=0 and ZF=0)
0F 88 cw/cd JS rel16/32 Jump near if sign (SF=1)
0F 89 cw/cd JNS rel16/32 Jump near if not sign (SF=0)
0F 8A cw/cd JP rel16/32 Jump near if parity (PF=1)
0F 8A cw/cd JPE rel16/32 Jump near if parity even (PF=1)
0F 8B cw/cd JNP rel16/32 Jump near if not parity (PF=0)
0F 8B cw/cd JPO rel16/32 Jump near if parity odd (PF=0)
0F 8C cw/cd JL rel16/32 Jump near if less (SF<>OF)
0F 8C cw/cd JNGE rel16/32 Jump near if not greater or equal (SF<>OF)
0F 8D cw/cd JGE rel16/32 Jump near if greater or equal (SF=OF)
0F 8D cw/cd JNL rel16/32 Jump near if not less (SF=OF)
0F 8E cw/cd JLE rel16/32 Jump near if less or equal (ZF=1 or SF<>OF)
0F 8E cw/cd JNG rel16/32 Jump near if not greater (ZF=1 or SF<>OF)
0F 8F cw/cd JG rel16/32 Jump near if greater (ZF=0 and SF=OF)
0F 8F cw/cd JNLE rel16/32 Jump near if not less or equal (ZF=0 and SF=OF)
0F 90 SETO r/m8 Set byte if overflow (OF=1)
0F 91 SETNO r/m8 Set byte if not overflow (OF=0)
0F 92 SETB r/m8 Set byte if below (CF=1)
0F 92 SETC r/m8 Set if carry (CF=1)
0F 92 SETNAE r/m8 Set byte if not above or equal (CF=1)
0F 93 SETAE r/m8 Set byte if above or equal (CF=0)
0F 93 SETNB r/m8 Set byte if not below (CF=0)
0F 93 SETNC r/m8 Set byte if not carry (CF=0)
0F 94 SETE r/m8 Set byte if equal (ZF=1)
0F 94 SETZ r/m8 Set byte if zero (ZF=1)
0F 95 SETNE r/m8 Set byte if not equal (ZF=0)
0F 95 SETNZ r/m8 Set byte if not zero (ZF=0)
0F 96 SETBE r/m8 Set byte if below or equal (CF=1 or ZF=1)
0F 96 SETNA r/m8 Set byte if not above (CF=1 or ZF=1)
0F 97 SETA r/m8 Set byte if above (CF=0 and ZF=0)
0F 97 SETNBE r/m8 Set byte if not below or equal (CF=0 and ZF=0)
0F 98 SETS r/m8 Set byte if sign (SF=1)
0F 99 SETNS r/m8 Set byte if not sign (SF=0)
0F 9A SETP r/m8 Set byte if parity (PF=1)
0F 9A SETPE r/m8 Set byte if parity even (PF=1)
0F 9B SETNP r/m8 Set byte if not parity (PF=0)
0F 9B SETPO r/m8 Set byte if parity odd (PF=0)
0F 9C SETL r/m8 Set byte if less (SF<>OF)
0F 9C SETNGE r/m8 Set if not greater or equal (SF<>OF)
0F 9D SETGE r/m8 Set byte if greater or equal (SF=OF)
0F 9D SETNL r/m8 Set byte if not less (SF=OF)
0F 9E SETLE r/m8 Set byte if less or equal (ZF=1 or SF<>OF)
0F 9E SETNG r/m8 Set byte if not greater (ZF=1 or SF<>OF)
0F 9F SETG r/m8 Set byte if greater (ZF=0 and SF=OF)
0F 9F SETNLE r/m8 Set byte if not less or equal (ZF=0 and SF=OF)
0F A0 PUSH FS Push FS
0F A1 POP FS Pop top of stack into FS; increment stack pointer
0F A2 CPUID Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, according to the input value entered initially in the EAX register
0F A3 BT r/m16,r16 Store selected bit in CF flag
0F A3 BT r/m32,r32 Store selected bit in CF flag
0F A4 SHLD r/m16, r16, imm8 Shift r/m16 to left imm8 places while shifting bits from r16 in from the right
0F A4 SHLD r/m32, r32, imm8 Shift r/m32 to left imm8 places while shifting bits from r32 in from the right
0F A5 SHLD r/m16, r16, CL Shift r/m16 to left CL places while shifting bits from r16 in from the right
0F A5 SHLD r/m32, r32, CL Shift r/m32 to left CL places while shifting bits from r32 in from the right
0F A8 PUSH GS Push GS
0F A9 POP GS Pop top of stack into GS; increment stack pointer
0F AA RSM Resume operation of interrupted program
0F AB BTS r/m16,r16 Store selected bit in CF flag and set
0F AB BTS r/m32,r32 Store selected bit in CF flag and set
0F AC SHRD r/m16, r16, imm8 Shift r/m16 to right imm8 places while shifting bits from r16 in from the left
0F AC SHRD r/m32, r32, mm8 Shift r/m32 to right imm8 places while shifting bits from r32 in from the left
0F AD SHRD r/m16, r16, CL Shift r/m16 to right CL places while shifting bits from r16 in from the left
0F AD SHRD r/m32, r32, CL Shift r/m32 to right CL places while shifting bits from r32 in from the left
0F AE /0 FXSAVE m512byte Save the x87 FPU, MMX technology, XMM, and MXCSR register state to m512byte.
0F AE /1 FXRSTOR m512byte Restore the x87 FPU, MMX technology, XMM, and MXCSR register state from m512byte.
0F AE /2 LDMXCSR m32 Load MXCSR register from m32.
0F AE /3 STMXCSR m32 Store contents of MXCSR register to m32.
0F AE /5 LFENCE Serializes load operations.
0F AE /6 MFENCE Serializes load and store operations.
0F AE /7 CLFLUSH m8 Flushes cache line containing m8.
0F AE /7 SFENCE Serializes store operations.
0F AF /r IMUL r16,r/m16 word register <- word register * r/m word
0F AF /r IMUL r32,r/m32 doubleword register <- doubleword register * r/m doubleword
0F B0 /r CMPXCHG r/m8,r8 Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL.
0F B1 /r CMPXCHG r/m16,r16 Compare AX with r/m16. If equal, ZF is set and r16 is loaded into r/m16. Else, clear ZF and load r/m16 into AL
0F B1 /r CMPXCHG r/m32,r32 Compare EAX with r/m32. If equal, ZF is set and r32 is loaded into r/m32. Else, clear ZF and load r/m32 into AL
0F B2 /r LSS r16,m16:16 Load SS: r16 with far pointer from memory
0F B2 /r LSS r32,m16:32 Load SS: r32 with far pointer from memory
0F B3 BTR r/m16,r16 Store selected bit in CF flag and clear
0F B3 BTR r/m32,r32 Store selected bit in CF flag and clear
0F B4 /r LFS r16,m16:16 Load FS: r16 with far pointer from memory
0F B4 /r LFS r32,m16:32 Load FS: r32 with far pointer from memory
0F B5 /r LGS r16,m16:16 Load GS: r16 with far pointer from memory
0F B5 /r LGS r32,m16:32 Load GS: r32 with far pointer from memory
0F B6 /r MOVZX r16,r/m8 Move byte to word with zero-extension
0F B6 /r MOVZX r32,r/m8 Move byte to doubleword, zero-extension
0F B7 /r MOVZX r32,r/m16 Move word to doubleword, zero-extension
0F BA /4 ib BT r/m16,imm8 Store selected bit in CF flag
0F BA /4 ib BT r/m32,imm8 Store selected bit in CF flag
0F BA /5 ib BTS r/m16,imm8 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m32,imm8 Store selected bit in CF flag and set
0F BA /6 ib BTR r/m16,imm8 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m32,imm8 Store selected bit in CF flag and clear
0F BA /7 ib BTC r/m16,imm8 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m32,imm8 Store selected bit in CF flag and complement
0F BB BTC r/m16,r16 Store selected bit in CF flag and complement
0F BB BTC r/m32,r32 Store selected bit in CF flag and complement
0F BC BSF r16,r/m16 Bit scan forward on r/m16
0F BC BSF r32,r/m32 Bit scan forward on r/m32
0F BD BSR r16,r/m16 Bit scan reverse on r/m16
0F BD BSR r32,r/m32 Bit scan reverse on r/m32
0F BE /r MOVSX r16,r/m8 Move byte to word with sign-extension
0F BE /r MOVSX r32,r/m8 Move byte to doubleword, sign-extension
0F BF /r MOVSX r32,r/m16 Move word to doubleword, sign-extension
0F C0 /r XADD r/m8, r8 Exchange r8 and r/m8; load sum into r/m8.
0F C1 /r XADD r/m16, r16 Exchange r16 and r/m16; load sum into r/m16.
0F C1 /r XADD r/m32, r32 Exchange r32 and r/m32; load sum into r/m32.
0F C2 /r ib CMPPS xmm1, xmm2/m128, imm8 Compare packed single-precision floating-point values in xmm2/mem and xmm1 using imm8 as comparison predicate.
0F C3 /r MOVNTI m32, r32 Move doubleword from r32 to m32 using non-temporal hint.
0F C4 /r ib PINSRW mm, r32/m16, imm8 Insert the low word from r32 or from m16 into mm at the word position specified by imm8
0F C5 /r ib PEXTRW r32, mm, imm8 Extract the word specified by imm8 from mm and move it to r32.
0F C6 /r ib SHUFPS xmm1, xmm2/m128, imm8 Shuffle packed single-precision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1.
0F C7 /1 m64 CMPXCHG8B m64 Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.
0F C8+rd BSWAP r32 Reverses the byte order of a 32-bit register.
0F D1 /r PSRLW mm, mm/m64 Shift words in mm right by amount specified in mm/m64 while shifting in zeros.
0F D2 /r PSRLD mm, mm/m64 Shift doublewords in mm right by amount specified in mm/m64 while shifting in zeros.
0F D3 /r PSRLQ mm, mm/m64 Shift mm right by amount specified in mm/m64 while shifting in zeros.
0F D4 /r PADDQ mm1,mm2/m64 Add quadword integer mm2/m64 to mm1
0F D5 /r PMULLW mm, mm/m64 Multiply the packed words in mm with the packed words in mm/m64, then store the low-order word of each doubleword result in mm.
0F D7 /r PMOVMSKB r32, mm Move a byte mask of mm to r32.
0F D8 /r PSUBUSB mm, mm/m64 Subtract unsigned packed bytes in mm/m64 from unsigned packed bytes in mm and saturate.
0F D9 /r PSUBUSW mm, mm/m64 Subtract unsigned packed words in mm/m64 from unsigned packed words in mm and saturate.
0F DA /r PMINUB mm1, mm2/m64 Compare unsigned byte integers in mm2/m64 and mm1 and returns minimum values.
0F DB /r PAND mm, mm/m64 AND quadword from mm/m64 to quadword in mm.
0F DC /r PADDUSB mm, mm/m64 Add unsigned packed bytes from mm/m64 to unsigned packed bytes in mm and saturate.
0F DD /r PADDUSW mm, mm/m64 Add unsigned packed words from mm/m64 to unsigned packed words in mm and saturate.
0F DE /r PMAXUB mm1, mm2/m64 Compare unsigned byte integers in mm2/m64 and mm1 and returns maximum values.
0F DF /r PANDN mm, mm/m64 AND quadword from mm/m64 to NOT quadword in mm.
0F E0 /r PAVGB mm1, mm2/m64 Average packed unsigned byte integers from mm2/m64 and mm1 with rounding.
0F E1 /r PSRAW mm, mm/m64 Shift words in mm right by amount specified in mm/m64 while shifting in sign bits.
0F E2 /r PSRAD mm, mm/m64 Shift doublewords in mm right by amount specified in mm/m64 while shifting in sign bits.
0F E3 /r PAVGW mm1, mm2/m64 Average packed unsigned word integers from mm2/m64 and mm1 with rounding.
0F E4 /r PMULHUW mm1, mm2/m64 Multiply the packed unsigned word integers in mm1 register and mm2/m64, and store the high 16 bits of the results in mm1.
0F E5 /r PMULHW mm, mm/m64 Multiply the signed packed words in mm by the signed packed words in mm/m64, then store the high-order word of each doubleword result in mm.
0F E7 /r MOVNTQ m64, mm Move quadword from mm to m64 using non-temporal hint.
0F E8 /r PSUBSB mm, mm/m64 Subtract signed packed bytes in mm/m64 from signed packed bytes in mm and saturate.
0F E9 /r PSUBSW mm, mm/m64 Subtract signed packed words in mm/m64 from signed packed words in mm and saturate.
0F EA /r PMINSW mm1, mm2/m64 Compare signed word integers in mm2/m64 and mm1 and return minimum values.
0F EC /r PADDSB mm, mm/m64 Add signed packed bytes from mm/m64 to signed packed bytes in mm and saturate.
0F EB /r POR mm, mm/m64 OR quadword from mm/m64 to quadword in mm.
0F ED /r PADDSW mm, mm/m64 Add signed packed words from mm/m64 to signed packed words in mm and saturate.
0F EE /r PMAXSW mm1, mm2/m64 Compare signed word integers in mm2/m64 and mm1 and return maximum values.
0F EF /r PXOR mm, mm/m64 XOR quadword from mm/m64 to quadword in mm.
0F F1 /r PSLLW mm, mm/m64 Shift words in mm left by amount specified in mm/m64, while shifting in zeros.
0F F2 /r PSLLD mm, mm/m64 Shift doublewords in mm left by amount specified in mm/m64, while shifting in zeros.
0F F3 /r PSLLQ mm, mm/m64 Shift mm left by amount specified in mm/m64, while shifting in zeros.
0F F4 /r PMULUDQ mm1, mm2/m64 Multiply unsigned doubleword integer in mm1 by unsigned doubleword integer in mm2/m64, and store the quadword result in mm1.
0F F5 /r PMADDWD mm, mm/m64 Multiply the packed words in mm by the packed words in mm/m64. Add the 32-bit pairs of results and store in mm as doubleword
0F F6 /r PSADBW mm1, mm2/m64 Computes the absolute differences of the packed unsigned byte integers from mm2 /m64 and mm1; differences are then summed to produce an unsigned word integer result.
0F F7 /r MASKMOVQ mm1, mm2 Selectively write bytes from mm1 to memory location using the byte mask in mm2
0F F8 /r PSUBB mm, mm/m64 Subtract packed bytes in mm/m64 from packed bytes in mm.
0F F9 /r PSUBW mm, mm/m64 Subtract packed words in mm/m64 from packed words in mm.
0F FA /r PSUBD mm, mm/m64 Subtract packed doublewords in mm/m64 from packed doublewords in mm.
0F FB /r PSUBQ mm1, mm2/m64 Subtract quadword integer in mm1 from mm2/m64.
0F FC /r PADDB mm, mm/m64 Add packed bytes from mm/m64 to packed bytes in mm.
0F FD /r PADDW mm, mm/m64 Add packed words from mm/m64 to packed words in mm.
0F FE /r PADDD mm, mm/m64 Add packed doublewords from mm/m64 to packed doublewords in mm.
10 /r ADC r/m8,r8 Add with carry byte register to r/m8
11 /r ADC r/m16,r16 Add with carry r16 to r/m16
11 /r ADC r/m32,r32 Add with CF r32 to r/m32
12 /r ADC r8,r/m8 Add with carry r/m8 to byte register
13 /r ADC r16,r/m16 Add with carry r/m16 to r16
13 /r ADC r32,r/m32 Add with CF r/m32 to r32
14 ib ADC AL, imm8 Add with carry imm8 to AL
15 iw ADC AX, imm16 Add with carry imm16 to AX
15 id ADC EAX, imm32 Add with carry imm32 to EAX
16 PUSH SS Push SS
17 POP SS Pop top of stack into SS; increment stack pointer
18 /r SBB r/m8,r8 Subtract with borrow r8 from r/m8
19 /r SBB r/m16,r16 Subtract with borrow r16 from r/m16
19 /r SBB r/m32,r32 Subtract with borrow r32 from r/m32
1A /r SBB r8,r/m8 Subtract with borrow r/m8 from r8
1B /r SBB r16,r/m16 Subtract with borrow r/m16 from r16
1B /r SBB r32,r/m32 Subtract with borrow r/m32 from r32
1C ib SBB AL, imm8 Subtract with borrow imm8 from AL
1D iw SBB AX, imm16 Subtract with borrow imm16 from AX
1D id SBB EAX, imm32 Subtract with borrow imm32 from EAX
1E PUSH DS Push DS
1F POP DS Pop top of stack into DS; increment stack pointer
20 /r AND r/m8,r8 r/m8 AND r8
21 /r AND r/m16,r16 r/m16 AND r16
21 /r AND r/m32,r32 r/m32 AND r32
22 /r AND r8,r/m8 r8 AND r/m8
23 /r AND r16,r/m16 r16 AND r/m16
23 /r AND r32,r/m32 r32 AND r/m32
24 ib AND AL, imm8 AL AND imm8
25 iw AND AX, imm16 AX AND i mm16
25 id AND EAX, imm32 EAX AND imm32
27 DAA Decimal adjust AL after addition
28 /r SUB r/m8,r8 Subtract r8 from r/m8
29 /r SUB r/m16,r16 Subtract r16 from r/m16
29 /r SUB r/m32,r32 Subtract r32 from r/m32
2A /r SUB r8,r/m8 Subtract r/m8 from r8
2B /r SUB r16,r/m16 Subtract r/m16 from r16
2B /r SUB r32,r/m32 Subtract r/m32 from r32
2C ib SUB AL,imm8 Subtract imm8 from AL
2D iw SUB AX,imm16 Subtract imm16 from AX
2D id SUB EAX,imm32 Subtract imm32 from EAX
2F DAS Decimal adjust AL after subtraction
30 /r XOR r/m8,r8 r/m8 XOR r8
31 /r XOR r/m16,r16 r/m16 XOR r16
31 /r XOR r/m32,r32 r/m32 XOR r32
32 /r XOR r8,r/m8 r8 XOR r/m8
33 /r XOR r16,r/m16 r16 XOR r/m16
33 /r XOR r32,r/m32 r32 XOR r/m32
34 ib XOR AL,imm8 AL XOR imm8
35 iw XOR AX,imm16 AX XOR imm16
35 id XOR EAX,imm32 EAX XOR imm32
37 AAA ASCII adjust AL after addition
38 /r CMP r/m8,r8 Compare r8 with r/m8
39 /r CMP r/m16,r16 Compare r16 with r/m16
39 /r CMP r/m32,r32 Compare r32 with r/m32
3A /r CMP r8,r/m8 Compare r/m8 with r8
3B /r CMP r16,r/m16 Compare r/m16 with r16
3B /r CMP r32,r/m32 Compare r/m32 with r32
3C ib CMP AL, imm8 Compare imm8 with AL
3D iw CMP AX, imm16 Compare imm16 with AX
3D id CMP EAX, imm32 Compare imm32 with EAX
3F AAS ASCII adjust AL after subtraction
40+rw INC r16 Increment word register by 1
40+rd INC r32 Increment doubleword register by 1
48+rw DEC r16 Decrement r16 by 1
48+rd DEC r32 Decrement r32 by 1
50+rw PUSH r16 Push r16
50+rd PUSH r32 Push r32
58+rw POP r16 Pop top of stack into r16; increment stack pointer
58+rd POP r32 Pop top of stack into r32; increment stack pointer
60 PUSHA Push AX, CX, DX, BX, original SP, BP, SI, and DI
60 PUSHAD Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI
61 POPA Pop DI, SI, BP, BX, DX, CX, and AX
61 POPAD Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX
62 /r BOUND r16,m16&16 Check if r16 (array index) is within bounds specified by m16&16
62 /r BOUND r32,m32&32 Check if r32 (array index) is within bounds specified by m16&16
63 /r ARPL r/m16,r16 Adjust RPL of r/m16 to not less than RPL of r16
66 0F 10 /r MOVUPD xmm1, xmm2/m128 Move packed double-precision floating-point values from xmm2/m128 to xmm1.
66 0F 11 /r MOVUPD xmm2/m128, xmm Move packed double-precision floating-point values from xmm1 to xmm2/m128.
66 0F 12 /r MOVLPD xmm, m64 Move double-precision floating-point value from m64 to low quadword of xmm register.
66 0F 13 /r MOVLPD m64, xmm Move double-precision floating-point nvalue from low quadword of xmm register to m64.
66 0F 14 /r UNPCKLPD xmm1, xmm2/m128 Unpacks and Interleaves double-precision floating-point values from low quadwords of xmm1 and xmm2/m128.
66 0F 15 /r UNPCKHPD xmm1, xmm2/m128 Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm1 and xmm2/m128.
66 0F 16 /r MOVHPD xmm, m64 Move double-precision floating-point value from m64 to high quadword of xmm.
66 0F 17 /r MOVHPD m64, xmm Move double-precision floating-point value from high quadword of xmm to m64.
66 0F 28 /r MOVAPD xmm1, xmm2/m128 Move packed double-precision floating-point values from xmm2/m128 to xmm1.
66 0F 29 /r MOVAPD xmm2/m128, xmm1 Move packed double-precision floating-point values from xmm1 to xmm2/m128.
66 0F 2A /r CVTPI2PD xmm, mm/m64 Convert two packed signed doubleword integers from mm/mem64 to two packed double-precision floating-point values in xmm.
66 0F 2B /r MOVNTPD m128, xmm Move packed double-precision floating-point values from xmm to m128 using non-temporal hint.
66 0F 2C /r CVTTPD2PI mm, xmm/m128 Convert two packer double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm using truncation.
66 0F 2D /r CVTPD2PI mm, xmm/m128 Convert two packed double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm.
66 0F 2E /r UCOMISD xmm1, xmm2/m64 Compares (unordered) the low double-precision floating-point values in xmm1 and xmm2/m64 and set the EFLAGS accordingly.
66 0F 2F /r COMISD xmm1, xmm2/m64 Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
66 0F 50 /r MOVMSKPD r32, xmm Extract 2-bit sign mask of from xmm and store in r32.
66 0F 51 /r SQRTPD xmm1, xmm2/m128 Computes square roots of the packed double-precision floating-point values in xmm2/m128 and stores the results in xmm1.
66 0F 54 /r ANDPD xmm1, xmm2/m128 Bitwise logical AND of xmm2/m128 and xmm1.
66 0F 55 /r ANDNPD xmm1, xmm2/m128 Bitwise logical AND NOT of xmm2/m128 and xmm1.
66 0F 56 /r ORPD xmm1, xmm2/m128 Bitwise OR of xmm2/m128 and xmm1.
66 0F 57 /r XORPD xmm1, xmm2/m128 Bitwise exclusive-OR of xmm2/m128 and xmm1
66 0F 58 /r ADDPD xmm1, xmm2/m128 Add packed double-precision floating-point values from xmm2/m128 to xmm1.
66 0F 59 /r MULPD xmm1, xmm2/m128 Multiply packed double-precision floating-point values in xmm2/m128 by xmm1.
66 0F 5A /r CVTPD2PS xmm1, xmm2/m128 Convert two packed double-precision floating-point values in xmm2/m128 to two packed single-precision floating-point values in xmm1.
66 0F 5B /r CVTPS2DQ xmm1, xmm2/m128 Convert four packed single-precision floating-point values from xmm2/m128 to four packed signed doubleword integers in xmm1.
66 0F 5C /r SUBPD xmm1, xmm2/m128 Subtract packed double-precision floating-point values in xmm2/m128 from xmm1.
66 0F 5D /r MINPD xmm1, xmm2/m128 Return the minimum double-precision floating-point values between xmm2/m128 and xmm1.
66 0F 5E /r DIVPD xmm1, xmm2/m128 Divide packed double-precision floating-point values in xmm1 by packed double-precision floating-point values xmm2/m128.
66 0F 5F /r MAXPD xmm1, xmm2/m128 Return the maximum double-precision floating-point values between xmm2/m128 and xmm1.
66 0F 60 /r PUNPCKLBW xmm1, xmm2/m128 Interleave low-order bytes from xmm1 and xmm2/m128 into xmm1.
66 0F 61 /r PUNPCKLWD xmm1, xmm2/m128 Interleave low-order words from xmm1 and xmm2/m128 into xmm1.
66 0F 62 /r PUNPCKLDQ xmm1, xmm2/m128 Interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1.
66 0F 63 /r PACKSSWB xmm1, xmm2/m128 Converts 8 packed signed word integers from xmm1 and from xmm2/m128 into 16 packed signed byte integers in xmm1 using signed saturation.
66 0F 64 /r PCMPGTB xmm1, xmm2/m128 Compare packed signed byte integers in xmm1 and xmm2/m128 for greater than.
66 0F 65 /r PCMPGTW xmm1, xmm2/m128 Compare packed signed word integers in xmm1 and xmm2/m128 for greater than.
66 0F 66 /r PCMPGTD xmm1, xmm2/m128 Compare packed signed doubleword integers in xmm1 and xmm2/m128 for greater than.
66 0F 67 /r PACKUSWB xmm1, xmm2/m128 Converts 8 signed word integers from xmm1 and 8 signed word integers from xmm2/m128 into 16 unsigned byte integers in xmm1 using unsigned saturation.
66 0F 68 /r PUNPCKHBW xmm1, xmm2/m128 Unpack and interleave high-order bytes from xmm1 and xmm2/m128 into xmm1.
66 0F 69 /r PUNPCKHWD xmm1, xmm2/m128 Unpack and interleave high-order words from xmm1 and xmm2/m128 into xmm1.
66 0F 6A /r PUNPCKHDQ xmm1, xmm2/m128 Unpack and interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1.
66 0F 6B /r PACKSSDW xmm1, xmm2/m128 Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 packed signed word integers in xmm1 using signed saturation.
66 0F 6C /r PUNPCKLQDQ xmm1, xmm2/m128 Interleave low-order quadwords from xmm1 and xmm2/m128 into xmm1 register
66 0F 6D /r PUNPCKHQDQ xmm1, xmm2/m128 Unpack and interleave high-order quadwords from xmm1 and xmm2/m128 into xmm1
66 0F 6E /r MOVD xmm, r/m32 Move doubleword from r/m32 to xmm.
66 0F 6F /r MOVDQA xmm1, xmm2/m128 Move aligned double quadword from xmm2/m128 to xmm1.
66 0F 70 /r ib PSHUFD xmm1, xmm2/m128, imm8 Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.
66 0F 71 /2 ib PSRLW xmm1, imm8 Shift words in xmm1 right by imm8 while shifting in 0s.
66 0F 71 /4 ib PSRAW xmm1, imm8 Shift words in xmm1 right by imm8 while shifting in sign bits
66 0F 71 /6 ib PSLLW xmm1, imm8 Shift words in xmm1 left by imm8 while shifting in 0s.
66 0F 72 /2 ib PSRLD xmm1, imm8 Shift doublewords in xmm1 right by imm8 while shifting in 0s.
66 0F 72 /4 ib PSRAD xmm1, imm8 Shift doublewords in xmm1 right by imm8 while shifting in sign bits.
66 0F 72 /6 ib PSLLD xmm1, imm8 Shift doublewords in xmm1 left by imm8 while shifting in 0s.
66 0F 73 /2 ib PSRLQ xmm1, imm8 Shift quadwords in xmm1 right by imm8 while shifting in 0s.
66 0F 73 /3 ib PSRLDQ xmm1, imm8 Shift xmm1 right by imm8 while shifting in 0s.
66 0F 73 /6 ib PSLLQ xmm1, imm8 Shift quadwords in xmm1 left by imm8 while shifting in 0s.
66 0F 73 /7 ib PSLLDQ xmm1, imm8 Shift xmm1 left by imm8 bytes while shifting in 0s.
66 0F 74 /r PCMPEQB xmm1, xmm2/m128 Compare packed bytes in xmm2/m128 and xmm1 for equality.
66 0F 75 /r PCMPEQW xmm1, xmm2/m128 Compare packed words in xmm2/m128 and xmm1 for equality.
66 0F 76 /r PCMPEQD xmm1, xmm2/m128 Compare packed doublewords in xmm2/m128 and xmm1 for equality.
66 0F 7E /r MOVD r/m32, xmm Move doubleword from xmm register to r/m32.
66 0F 7F /r MOVDQA xmm2/m128, xmm1 Move aligned double quadword from xmm1 to xmm2/m128.
66 0F C2 /r ib CMPPD xmm1, xmm2/m128, imm8 Compare packed double-precision floating-point values in xmm2/m128 and xmm1 using imm8 as comparison predicate.
66 0F C4 /r ib PINSRW xmm, r32/m16, imm8 Move the low word of r32 or from m16 into xmm at the word position specified by imm8.
66 0F C5 /r ib PEXTRW r32, xmm, imm8 Extract the word specified by imm8 from xmm and move it to a r32.
66 0F C6 /r ib SHUFPD xmm1, xmm2/m128, imm8 Shuffle packed double-precision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1.
66 0F D1 /r PSRLW xmm1, xmm2/m128 Shift words in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.
66 0F D2 /r PSRLD xmm1, xmm2/m128 Shift doublewords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.
66 0F D3 /r PSRLQ xmm1, xmm2/m128 Shift quadwords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.
66 0F D4 /r PADDQ xmm1,xmm2/m128 Add packed quadword integers xmm2/m128 to xmm1
66 0F D5 /r PMULLW xmm1, xmm2/m128 Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of the results in xmm1.
66 0F D6 MOVQ xmm2/m64, xmm1 Move quadword from xmm1 to xmm2/mem64.
66 0F D7 /r PMOVMSKB r32, xmm Move a byte mask of xmm to r32.
66 0F D8 /r PSUBUSB xmm1, xmm2/m128 Subtract packed unsigned byte integers in xmm2/m128 from packed unsigned byte integers in xmm1 and saturate result.
66 0F D9 /r PSUBUSW xmm1, xmm2/m128 Subtract packed unsigned word integers in xmm2/m128 from packed unsigned word integers in xmm1 and saturate result.
66 0F DA /r PMINUB xmm1, xmm2/m128 Compare unsigned byte integers in xmm2/m128 and xmm1 and returns minimum values.
66 0F DB /r PAND xmm1, xmm2/m128 Bitwise AND of xmm2/m128 and xmm1.
66 0F DC /r PADDUSB xmm1, xmm2/m128 Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results.
66 0F DD /r PADDUSW xmm1, xmm2/m128 Add packed unsigned word integers from xmm2/m128 to xmm1 and saturate the results.
66 0F DE /r PMAXUB xmm1, xmm2/m128 Compare unsigned byte integers in xmm2/m128 and xmm1 and returns maximum values.
66 0F DF /r PANDN xmm1, xmm2/m128 Bitwise AND NOT of xmm2/m128 and xmm1.
66 0F E0 /r PAVGB xmm1, xmm2/m128 Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding.
66 0F E1 /r PSRAW xmm1, xmm2/m128 Shift words in xmm1 right by xmm2/m128 while shifting in sign bits.
66 0F E2 /r PSRAD xmm1, xmm2/m128 Shift doubleword in xmm1 right by xmm2/m128 while shifting in sign bits.
66 0F E3 /r PAVGW xmm1, xmm2/m128 Average packed unsigned word integers from xmm2/m128 and xmm1 with rounding.
66 0F E4 /r PMULHUW xmm1, xmm2/m128 Multiply the packed unsigned word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.
66 0F E5 /r PMULHW xmm1, xmm2/m128 Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.
66 0F E6 CVTTPD2DQ xmm1, xmm2/m128 Convert two packed double-precision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1 using truncation.
66 0F E7 /r MOVNTDQ m128, xmm Move double quadword from xmm to m128 using non-temporal hint.
66 0F E8 /r PSUBSB xmm1, xmm2/m128 Subtract packed signed byte integers in xmm2/m128 from packed signed byte integers in xmm1 and saturate results.
66 0F E9 /r PSUBSW xmm1, xmm2/m128 Subtract packed signed word integers in xmm2/m128 from packed signed word integers in xmm1 and saturate results.
66 0F EA /r PMINSW xmm1, xmm2/m128 Compare signed word integers in xmm2/m128 and xmm1 and return minimum values.
66 0F EB /r POR xmm1, xmm2/m128 Bitwise OR of xmm2/m128 and xmm1.
66 0F EC /r PADDSB xmm1, xmm2/m128 Add packed signed byte integers from xmm2/m128 and xmm1 saturate the results.
66 0F ED /r PADDSW xmm1, xmm2/m128 Add packed signed word integers from xmm2/m128 and xmm1 and saturate the results.
66 0F EE /r PMAXSW xmm1, xmm2/m128 Compare signed word integers in xmm2/m128 and xmm1 and return maximum values.
66 0F EF /r PXOR xmm1, xmm2/m128 Bitwise XOR of xmm2/m128 and xmm1.
66 0F F1 /r PSLLW xmm1, xmm2/m128 Shift words in xmm1 left by xmm2/m128 while shifting in 0s.
66 0F F2 /r PSLLD xmm1, xmm2/m128 Shift doublewords in xmm1 left by xmm2/m128 while shifting in 0s.
66 0F F3 /r PSLLQ xmm1, xmm2/m128 Shift quadwords in xmm1 left by xmm2/m128 while shifting in 0s.
66 0F F4 /r PMULUDQ xmm1, xmm2/m128 Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers in xmm2/m128, and store the quadword results in xmm1.
66 0F F5 /r PMADDWD xmm1, xmm2/m128 Multiply the packed word integers in xmm1 by the packed word integers in xmm2/m128, add adjacent doubleword results, and store in xmm1.
66 0F F6 /r PSADBW xmm1, xmm2/m128 Computes the absolute differences of the packed unsigned byte integers from xmm2 /m128 and xmm1; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results.
66 0F F7 /r MASKMOVDQU xmm1, xmm2 Selectively write bytes from xmm1 to memory location using the byte mask in xmm2.
66 0F F8 /r PSUBB xmm1, xmm2/m128 Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1.
66 0F F9 /r PSUBW xmm1, xmm2/m128 Subtract packed word integers in xmm2/m128 from packed word integers in xmm1.
66 0F FA /r PSUBD xmm1, xmm2/m128 Subtract packed doubleword integers in xmm2/mem128 from packed doubleword integers in xmm1.
66 0F FB /r PSUBQ xmm1, xmm2/m128 Subtract packed quadword integers in xmm1 from xmm2 /m128.
66 0F FC /r PADDB xmm1, xmm2/m128 Add packed byte integers from xmm2/m128 and xmm1.
66 0F FD /r PADDW xmm1, xmm2/m128 Add packed word integers from xmm2/m128 and xmm1.
66 0F FE /r PADDD xmm1, xmm2/m128 Add packed doubleword integers from xmm2/m128 and xmm1.
68 PUSH imm16 Push imm16
68 PUSH imm32 Push imm32
69 /r iw IMUL r16,r/m16,imm16 word register <- r/m16 * immediate word
69 /r iw IMUL r16,imm16 word register <- r/m16 * immediate word
69 /r id IMUL r32,r/m32,imm32 doubleword register <- r/m32 * immediate doubleword
69 /r id IMUL r32,imm32 doubleword register <- r/m32 * immediate doubleword
6A PUSH imm8 Push imm8
6B /r ib IMUL r16,r/m16,imm8 word register <- r/m16 * sign-extended immediate byte
6B /r ib IMUL r32,r/m32,imm8 doubleword register <- r/m32 * sign-extended immediate byte
6B /r ib IMUL r16,imm8 word register <- word register * sign-extended immediate byte
6B /r ib IMUL r32,imm8 doubleword register <- doubleword register * sign-extended immediate byte
6C INS m8, DX Input byte from I/O port specified in DX into memory location specified in ES:(E)DI
6C INSB Input byte from I/O port specified in DX into memory location specified with ES:(E)DI
6D INS m16, DX Input word from I/O port specified in DX into memory location specified in ES:(E)DI
6D INS m32, DX Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI
6D INSW Input word from I/O port specified in DX into memory location specified in ES:(E)DI
6D INSD Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI
6E OUTS DX, m8 Output byte from memory location specified in DS:(E)SI to I/O port specified in DX
6E OUTSB Output byte from memory location specified in DS:(E)SI to I/O port specified in DX
6F OUTS DX, m16 Output word8 from memory location specified in DS:(E)SI to I/O port specified in DX
6F OUTS DX, m32 Output doubleword from memory location specified in DS:(E)SI to I/O port specified in DX
6F OUTSW Output word from memory location specified in DS:(E)SI to I/O port specified in DX
6F OUTSD Output doubleword from memory location specified in DS:(E)SI to I/O port specified in DX
70 cb JO rel8 Jump short if overflow (OF=1)
71 cb JNO rel8 Jump short if not overflow (OF=0)
72 cb JB rel8 Jump short if below (CF=1)
72 cb JC rel8 Jump short if carry (CF=1) (CF=0)
73 cb JNB rel8 Jump short if not below (CF=0)
73 cb JNC rel8 Jump short if not carry (CF=0)
74 cb JE rel8 Jump short if equal (ZF=1)
74 cb JZ rel8 Jump short if zero (ZF = 1)
75 cb JNE rel8 Jump short if not equal (ZF=0)
75 cb JNZ rel8 Jump short if not zero (ZF=0)
76 cb JBE rel8 Jump short if below or equal (CF=1 or ZF=1)
76 cb JNA rel8 Jump short if not above (CF=1 or ZF=1)
77 cb JA rel8 Jump short if above (CF=0 and ZF=0)
77 cb JNBE rel8 Jump short if not below or equal (CF=0 and ZF=0)
78 cb JS rel8 Jump short if sign (SF=1)
79 cb JNS rel8 Jump short if not sign (SF=0)
7A cb JP rel8 Jump short if parity (PF=1)
7A cb JPE rel8 Jump short if parity even (PF=1)
7B cb JNP rel8 Jump short if not parity (PF=0)
7B cb JPO rel8 Jump short if parity odd (PF=0)
78 cb JS rel8 Jump short if sign (SF=1)
7C cb JL rel8 Jump short if less (SF<>OF)
7C cb JNGE rel8 Jump short if not greater or equal (SF<>OF)
7D cb JGE rel8 Jump short if greater or equal (SF=OF)
7D cb JNL rel8 Jump short if not less (SF=OF)
7E cb JLE rel8 Jump short if less or equal (ZF=1 or SF<>OF)
7E cb JNG rel8 Jump short if not greater (ZF=1 or SF<>OF)
7F cb JG rel8 Jump short if greater (ZF=0 and SF=OF)
7F cb JNLE rel8 Jump short if not less or equal (ZF=0 and SF=OF)
80 /0 ib ADD r/m8,imm8 Add imm8 to r/m8
80 /1 ib OR r/m8,imm8 r/m8 OR imm8
80 /2 ib ADC r/m8,imm8 Add with carry imm8 to r/m8
80 /3 ib SBB r/m8,imm8 Subtract with borrow imm8 from r/m8
80 /4 ib AND r/m8,imm8 r/m8 AND imm8
80 /5 ib SUB r/m8,imm8 Subtract imm8 from r/m8
80 /6 ib XOR r/m8,imm8 r/m8 XOR imm8
80 /7 ib CMP r/m8, imm8 Compare imm8 with r/m8
81 /0 iw ADD r/m16,imm16 Add imm16 to r/m16
81 /0 id ADD r/m32,imm32 Add imm32 to r/m32
81 /1 iw OR r/m16,imm16 r/m16 OR imm16
81 /1 id OR r/m32,imm32 r/m32 OR imm32
81 /2 iw ADC r/m16,imm16 Add with carry imm16 to r/m16
81 /2 id ADC r/m32,imm32 Add with CF imm32 to r/m32
81 /3 iw SBB r/m16,imm16 Subtract with borrow imm16 from r/m16
81 /3 id SBB r/m32,imm32 Subtract with borrow imm32 from r/m32
81 /4 iw AND r/m16,imm16 r/m16 AND imm16
81 /4 id AND r/m32,imm32 r/m32 AND imm32
81 /5 iw SUB r/m16,imm16 Subtract imm16 from r/m16
81 /5 id SUB r/m32,imm32 Subtract imm32 from r/m32
81 /6 iw XOR r/m16,imm16 r/m16 XOR imm16
81 /6 id XOR r/m32,imm32 r/m32 XOR imm32
81 /7 iw CMP r/m16, imm16 Compare imm16 with r/m16
81 /7 id CMP r/m32,imm32 Compare imm32 with r/m32
83 /0 ib ADD r/m16,imm8 Add sign-extended imm8 to r/m16
83 /0 ib ADD r/m32,imm8 Add sign-extended imm8 to r/m32
83 /1 ib OR r/m16,imm8 r/m16 OR imm8 (sign-extended)
83 /1 ib OR r/m32,imm8 r/m32 OR imm8 (sign-extended)
83 /2 ib ADC r/m16,imm8 Add with CF sign-extended imm8 to r/m16
83 /2 ib ADC r/m32,imm8 Add with CF sign-extended imm8 into r/m32
83 /3 ib SBB r/m16,imm8 Subtract with borrow sign-extended imm8 from r/m16
83 /3 ib SBB r/m32,imm8 Subtract with borrow sign-extended imm8 from r/m32
83 /4 ib AND r/m16,imm8 r/m16 AND imm8 (sign-extended)
83 /4 ib AND r/m32,imm8 r/m32 AND imm8 (sign-extended)
83 /5 ib SUB r/m16,imm8 Subtract sign-extended imm8 from r/m16
83 /5 ib SUB r/m32,imm8 Subtract sign-extended imm8 from r/m32
83 /6 ib XOR r/m16,imm8 r/m16 XOR imm8 (sign-extended)
83 /6 ib XOR r/m32,imm8 r/m32 XOR imm8 (sign-extended)
83 /7 ib CMP r/m16,imm8 Compare imm8 with r/m16
83 /7 ib CMP r/m32,imm8 Compare imm8 with r/m32
84 /r TEST r/m8,r8 AND r8 with r/m8; set SF, ZF, PF according to result
85 /r TEST r/m16,r16 AND r16 with r/m16; set SF, ZF, PF according to result
85 /r TEST r/m32,r32 AND r32 with r/m32; set SF, ZF, PF according to result
86 /r XCHG r/m8, r8 Exchange r8 (byte register) with byte from r/m8
86 /r XCHG r8, r/m8 Exchange byte from r/m8 with r8 (byte register)
87 /r XCHG r/m16, r16 Exchange r16 with word from r/m16
87 /r XCHG r16, r/m16 Exchange word from r/m16 with r16
87 /r XCHG r/m32, r32 Exchange r32 with doubleword from r/m32
87 /r XCHG r32, r/m32 Exchange doubleword from r/m32 with r32
88 /r MOV r/m8,r8 Move r8 to r/m8
89 /r MOV r/m16,r16 Move r16 to r/m16
89 /r MOV r/m32,r32 Move r32 to r/m32
8A /r MOV r8,r/m8 Move r/m8 to r8
8B /r MOV r16,r/m16 Move r/m16 to r16
8B /r MOV r32,r/m32 Move r/m32 to r32
8C /r MOV r/m16,Sreg Move segment register to r/m16
8E /r MOV Sreg,r/m16 Move r/m16 to segment register
8D /r LEA r16,m Store effective address for m in register r16
8D /r LEA r32,m Store effective address for m in register r32
8F /0 POP m16 Pop top of stack into m16; increment stack pointer
8F /0 POP m32 Pop top of stack into m32; increment stack pointer
90 NOP No operation
90+rw XCHG AX, r16 Exchange r16 with AX
90+rw XCHG r16, AX Exchange AX with r16
90+rd XCHG EAX, r32 Exchange r32 with EAX
90+rd XCHG r32, EAX Exchange EAX with r32
98 CBW AX <- sign-extend of AL
98 CWDE EAX <- sign-extend of AX
99 CWD DX:AX <- sign-extend of AX
99 CDQ EDX:EAX -< sign-extend of EAX
9A cd CALL ptr16:16 Call far, absolute, address given in operand
9A cp CALL ptr16:32 Call far, absolute, address given in operand
9B WAIT Check pending unmasked floating-point exceptions.
9B FWAIT Check pending unmasked floating-point exceptions.
9B D9 /6 FSTENV m14/28byte Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions.
9B D9 /7 FSTCW m2byte Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions.
9B DB E2 FCLEX Clear floating-point exception flags after checking for pending unmasked floating-point exceptions.
9B DB E3 FINIT Initialize FPU after checking for pending unmasked floating-point exceptions.
9B DD /6 FSAVE m94/108byte Store FPU state to m94byte or m108byte after checking for pending unmasked floating-point exceptions. Then re-initialize the FPU.
9B DD /7 FSTSW m2byte Store FPU status word at m2byte after checking for pending unmasked floating-point exceptions.
9B DF E0 FSTSW AX Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.
9C PUSHF Push lower 16 bits of EFLAGS
9C PUSHFD Push EFLAGS
9D POPF Pop top of stack into lower 16 bits of EFLAGS
9D POPFD Pop top of stack into EFLAGS
9E SAHF Loads SF, ZF, AF, PF, and CF from AH into EFLAGS register. clocks=2
9F LAHF Load: AH = EFLAGS(SF:ZF:0:AF:0:PF:1:CF)
A0 MOV AL, moffs8 Move byte at ( seg:offset) to AL
A1 MOV AX, moffs16 Move word at ( seg:offset) to AX
A1 MOV EAX, moffs32 Move doubleword at ( seg:offset) to EAX
A2 MOV moffs8,AL Move AL to ( seg:offset)
A3 MOV moffs16,AX Move AX to ( seg:offset)
A3 MOV moffs32,EAX Move EAX to ( seg:offset)
A4 MOVS m8, m8 Move byte at address DS:(E)SI to address ES:(E)DI
A4 MOVSB Move byte at address DS:(E)SI to address ES:(E)DI
A5 MOVS m16, m16 Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVS m32, m32 Move doubleword at address DS:(E)SI to address ES:(E)DI
A5 MOVSW Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVSD Move doubleword at address DS:(E)SI to address ES:(E)DI
A6 CMPS m8, m8 Compares byte at address DS:(E)SI with byte at address ES:(E)DI and sets the status flags accordingly
A6 CMPSB Compares byte at address DS:(E)SI with byte at address ES:(E)DI and sets the status flags accordingly
A7 CMPS m16, m16 Compares word at address DS:(E)SI with word at address ES:(E)DI and sets the status flags accordingly
A7 CMPS m32, m32 Compares doubleword at address DS:(E)SI with doubleword at address ES:(E)DI and sets the status flags accordingly
A7 CMPSW Compares word at address DS:(E)SI with word at address ES:(E)DI and sets the status flags accordingly
A7 CMPSD Compares doubleword at address DS:(E)SI with doubleword at address ES:(E)DI and sets the status flags accordingly
A8 ib TEST AL,imm8 AND imm8 with AL; set SF, ZF, PF according to result
A9 iw TEST AX,imm16 AND imm16 with AX; set SF, ZF, PF according to result
A9 id TEST EAX,imm32 AND imm32 with EAX; set SF, ZF, PF according to result
AA STOS m8 Store AL at address ES:(E)DI
AB STOS m16 Store AX at address ES:(E)DI
AB STOS m32 Store EAX at address ES:(E)DI
AA STOSB Store AL at address ES:(E)DI
AB STOSW Store AX at address ES:(E)DI
AB STOSD Store EAX at address ES:(E)DI
AC LODS m8 Load byte at address DS:(E)SI into AL
AC LODSB Load byte at address DS:(E)SI into AL
AD LODS m16 Load word at address DS:(E)SI into AX
AD LODS m32 Load doubleword at address DS:(E)SI into EAX
AD LODSW Load word at address DS:(E)SI into AX
AD LODSD Load doubleword at address DS:(E)SI into EAX
AE SCAS m8 Compare AL with byte at ES:(E)DI and set status flags
AE SCASB Compare AL with byte at ES:(E)DI and set status flags
AF SCAS m16 Compare AX with word at ES:(E)DI and set status flags
AF SCAS m32 Compare EAX with doubleword at ES(E)DI and set status flags
AF SCASW Compare AX with word at ES:(E)DI and set status flags
AF SCASD Compare EAX with doubleword at ES:(E)DI and set status flags
B0+rb MOV r8,imm8 Move imm8 to r8
B8+rw MOV r16,imm16 Move imm16 to r16
B8+rd MOV r32,imm32 Move imm32 to r32
C0 /0 ib ROL r/m8,imm8 Rotate 8 bits r/m8 left imm8 times
C0 /1 ib ROR r/m8,imm8 Rotate 8 bits r/m16 right imm8 times
C0 /2 ib RCL r/m8,imm8 Rotate 9 bits (CF, r/m8) left imm8 times
C0 /3 ib RCR r/m8,imm8 Rotate 9 bits (CF, r/m8) right imm8 times
C0 /4 ib SAL r/m8,imm8 Multiply r/m8 by 2, imm8 times
C0 /4 ib SHL r/m8,imm8 Multiply r/m8 by 2, imm8 times
C0 /5 ib SHR r/m8,imm8 Unsigned divide r/m8 by 2, imm8 times
C0 /7 ib SAR r/m8,imm8 Signed divide r/m8 by 2, imm8 times
C1 /0 ib ROL r/m16,imm8 Rotate 16 bits r/m16 left imm8 times
C1 /0 ib ROL r/m32,imm8 Rotate 32 bits r/m32 left imm8 times
C1 /1 ib ROR r/m16,imm8 Rotate 16 bits r/m16 right imm8 times
C1 /1 ib ROR r/m32,imm8 Rotate 32 bits r/m32 right imm8 times
C1 /2 ib RCL r/m16,imm8 Rotate 17 bits (CF, r/m16) left imm8 times
C1 /2 ib RCL r/m32,imm8 Rotate 33 bits (CF, r/m32) left imm8 times
C1 /3 ib RCR r/m16,imm8 Rotate 17 bits (CF, r/m16) right imm8 times
C1 /3 ib RCR r/m32,imm8 Rotate 33 bits (CF, r/m32) right imm8 times
C1 /4 ib SAL r/m16,imm8 Multiply r/m16 by 2, imm8 times
C1 /4 ib SAL r/m32,imm8 Multiply r/m32 by 2, imm8 times
C1 /4 ib SHL r/m16,imm8 Multiply r/m16 by 2, imm8 times
C1 /4 ib SHL r/m32,imm8 Multiply r/m32 by 2, imm8 times
C1 /5 ib SHR r/m16,imm8 Unsigned divide r/m16 by 2, imm8 times
C1 /5 ib SHR r/m32,imm8 Unsigned divide r/m32 by 2, imm8 times
C1 /7 ib SAR r/m16,imm8 Signed divide r/m16 by 2, imm8 times
C1 /7 ib SAR r/m32,imm8 Signed divide r/m32 by 2, imm8 times
C2 iw RET imm16 Near return to calling procedure and pop imm16 bytes from stack
C3 RET Near return to calling procedure
C4 /r LES r16,m16:16 Load ES: r16 with far pointer from memory
C4 /r LES r32,m16:32 Load ES: r32 with far pointer from memory
C5 /r LDS r16,m16:16 Load DS: r16 with far pointer from memory
C5 /r LDS r32,m16:32 Load DS: r32 with far pointer from memory
C6 /0 MOV r/m8,imm8 Move imm8 to r/m8
C7 /0 MOV r/m16,imm16 Move imm16 to r/m16
C7 /0 MOV r/m32,imm32 Move imm32 to r/m32
C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
C8 iw 01 ENTER imm16,1 Create a nested stack frame for a procedure
C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a procedure
C9 LEAVE Set SP to BP, then pop BP
C9 LEAVE Set ESP to EBP, then pop EBP
CA iw RET imm16 Far return to calling procedure and pop imm16 bytes from stack
CB RET Far return to calling procedure
CC INT 3 Interrupt 3Чtrap to debugger
CD ib INT imm8 Interrupt vector number specified by immediate byte
CE INTO Interrupt 4Чif overflow flag is 1
CF IRET Interrupt return (16-bit operand size)
CF IRETD Interrupt return (32-bit operand size)
D0 /0 ROL r/m8,1 Rotate 8 bits r/m8 left once
D0 /1 ROR r/m8,1 Rotate 8 bits r/m8 right once
D0 /2 RCL r/m8,1 Rotate 9 bits (CF, r/m8) left once
D0 /3 RCR r/m8,1 Rotate 9 bits (CF, r/m8) right once
D0 /4 SAL r/m8,1 Multiply r/m8 by 2, once
D0 /4 SHL r/m8,1 Multiply r/m8 by 2, once
D0 /5 SHR r/m8,1 Unsigned divide r/m8 by 2, once
D0 /7 SAR r/m8,1 Signed divide r/m8 by 2, once
D1 /0 ROL r/m16,1 Rotate 16 bits r/m16 left once
D1 /0 ROL r/m32,1 Rotate 32 bits r/m32 left once
D1 /1 ROR r/m16,1 Rotate 16 bits r/m16 right once
D1 /1 ROR r/m32,1 Rotate 32 bits r/m32 right once
D1 /2 RCL r/m16,1 Rotate 17 bits (CF, r/m16) left once
D1 /2 RCL r/m32,1 Rotate 33 bits (CF, r/m32) left once
D1 /3 RCR r/m16,1 Rotate 17 bits (CF, r/m16) right once
D1 /3 RCR r/m32,1 Rotate 33 bits (CF, r/m32) right once
D1 /4 SAL r/m16,1 Multiply r/m16 by 2, once
D1 /4 SAL r/m32,1 Multiply r/m32 by 2, once
D1 /4 SHL r/m16,1 Multiply r/m16 by 2, once
D1 /4 SHL r/m32,1 Multiply r/m32 by 2, once
D1 /5 SHR r/m16,1 Unsigned divide r/m16 by 2, once
D1 /5 SHR r/m32,1 Unsigned divide r/m32 by 2, once
D1 /7 SAR r/m16,1 Signed divide r/m16 by 2, once
D1 /7 SAR r/m32,1 Signed divide r/m32 by 2, once
D2 /0 ROL r/m8,CL Rotate 8 bits r/m8 left CL times
D2 /1 ROR r/m8,CL Rotate 8 bits r/m8 right CL times
D2 /2 RCL r/m8,CL Rotate 9 bits (CF, r/m8) left CL times
D2 /3 RCR r/m8,CL Rotate 9 bits (CF, r/m8) right CL times
D2 /4 SAL r/m8,CL Multiply r/m8 by 2, CL times
D2 /4 SHL r/m8,CL Multiply r/m8 by 2, CL times
D2 /5 SHR r/m8,CL Unsigned divide r/m8 by 2, CL times
D2 /7 SAR r/m8,CL Signed divide r/m8 by 2, CL times
D3 /0 ROL r/m16,CL Rotate 16 bits r/m16 left CL times
D3 /0 ROL r/m32,CL Rotate 32 bits r/m32 left CL times
D3 /1 ROR r/m16,CL Rotate 16 bits r/m16 right CL times
D3 /1 ROR r/m32,CL Rotate 32 bits r/m32 right CL times
D3 /2 RCL r/m16,CL Rotate 17 bits (CF, r/m16) left CL times
D3 /2 RCL r/m32,CL Rotate 33 bits (CF, r/m32) left CL times
D3 /3 RCR r/m16,CL Rotate 17 bits (CF, r/m16) right CL times
D3 /3 RCR r/m32,CL Rotate 33 bits (CF, r/m32) right CL times
D3 /4 SAL r/m16,CL Multiply r/m16 by 2, CL times
D3 /4 SAL r/m32,CL Multiply r/m32 by 2, CL times
D3 /4 SHL r/m16,CL Multiply r/m16 by 2, CL times
D3 /4 SHL r/m32,CL Multiply r/m32 by 2, CL times
D3 /5 SHR r/m16,CL Unsigned divide r/m16 by 2, CL times
D3 /5 SHR r/m32,CL Unsigned divide r/m32 by 2, CL times
D3 /7 SAR r/m16,CL Signed divide r/m16 by 2, CL times
D3 /7 SAR r/m32,CL Signed divide r/m32 by 2, CL times
D4 0A AAM ASCII adjust AX after multiply
D4 ib (No mnemonic) Adjust AX after multiply to number base imm8
D5 0A AAD ASCII adjust AX before division
D5 ib (No mnemonic) Adjust AX before division to number base imm8
D7 XLAT m8 Set AL to memory byte DS:[(E)BX +unsigned AL]
D7 XLATB Set AL to memory byte DS:[(E)BX +unsigned AL]
D8 /0 FADD m32fp Add m32fp to ST(0) and store result in ST(0)
D8 /1 FMUL m32fp Multiply ST(0) by m32fp and store result in ST(0)
D8 /2 FCOM m32fp Compare ST(0) with m32fp.
D8 /3 FCOMP m32fp Compare ST(0) with m32fp and pop register stack.
D8 /4 FSUB m32fp Subtract m32fp from ST(0) and store result in ST(0)
D8 /5 FSUBR m32fp Subtract ST(0) from m32fp and store result in ST(0)
D8 /6 FDIV m32fp Divide ST(0) by m32fp and store result in ST(0)
D8 /7 FDIVR m32fp Divide m32fp by ST(0) and store result in ST(0)
D8 C0+i FADD ST(0), ST(i) Add ST(0) to ST(i) and store result in ST(0)
D8 C8+i FMUL ST(0), ST(i) Multiply ST(0) by ST(i) and store result in ST(0)
D8 D0+i FCOM ST(i) Compare ST(0) with ST(i).
D8 D1 FCOM Compare ST(0) with ST(1).
D8 D8+i FCOMP ST(i) Compare ST(0) with ST(i) and pop register stack.
D8 D9 FCOMP Compare ST(0) with ST(1) and pop register stack.
D8 E0+i FSUB ST(0), ST(i) Subtract ST(i) from ST(0) and store result in ST(0)
D8 E8+i FSUBR ST(0), ST(i) Subtract ST(0) from ST(i) and store result in ST(0)
D8 F0+i FDIV ST(0), ST(i) Divide ST(0) by ST(i) and store result in ST(0)
D8 F8+i FDIVR ST(0), ST(i) Divide ST(i) by ST(0) and store result in ST(0)
D9 /0 FLD m32fp Push m32fp onto the FPU register stack.
D9 /2 FST m32fp Copy ST(0) to m32fp
D9 /3 FSTP m32fp Copy ST(0) to m32fp and pop register stack
D9 /4 FLDENV m14/28byte Load FPU environment from m14byte or m28byte.
D9 /5 FLDCW m2byte Load FPU control word from m2byte.
D9 /6 FNSTENV m14/28byte Store FPU environment to m14byte or m28byte without checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions.
D9 /7 FNSTCW m2byte Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions.
D9 C0+i FLD ST(i) Push ST(i) onto the FPU register stack.
D9 C8+i FXCH ST(i) Exchange the contents of ST(0) and ST(i)
D9 C9 FXCH Exchange the contents of ST(0) and ST(1)
D9 D0 FNOP No operation is performed.
D9 E0 FCHS Complements sign of ST(0)
D9 E1 FABS Replace ST with its absolute value.
D9 E4 FTST Compare ST(0) with 0.0.
D9 E5 FXAM Classify value or number in ST(0)
D9 E8 FLD1 Push +1.0 onto the FPU register stack.
D9 E9 FLDL2T Push log2(10) onto the FPU register stack.
D9 EA FLDL2E Push log2(e) onto the FPU register stack.
D9 EB FLDPI Push p onto the FPU register stack.
D9 EC FLDLG2 Push log10(2) onto the FPU register stack.
D9 ED FLDLN2 Push loge(2) onto the FPU register stack.
D9 EE FLDZ Push +0.0 onto the FPU register stack.
D9 F0 F2XM1 Replace ST(0) with (2^ST(0) Ц 1)
D9 F1 FYL2X Replace ST(1) with (ST(1) * log2(ST(0))) and pop the register stack
D9 F2 FPTAN Replace ST(0) with its tangent and push 1 onto the FPU stack. clocks=17-173
D9 F3 FPATAN Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack
D9 F4 FXTRACT Separate value in ST(0) into exponent and significand, store exponent in ST(0), and push the significand onto the register stack.
D9 F5 FPREM1 Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1)
D9 F6 FDECSTP Decrement TOP field in FPU status word.
D9 F7 FINCSTP Increment the TOP field in the FPU status register
D9 F8 FPREM Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1)
D9 F9 FYL2XP1 Replace ST(1) with ST(1) * log2 (ST(0) + 1.0) and pop the register stack
D9 FA FSQRT Calculates square root of ST(0) and stores the result in ST(0)
D9 FB FSINCOS Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack.
D9 FC FRNDINT Round ST(0) to an integer.
D9 FD FSCALE Scale ST(0) by ST(1).
D9 FE FSIN Replace ST(0) with its sine.
D9 FF FCOS Replace ST(0) with its cosine
DA /0 FIADD m32int Add m32int to ST(0) and store result in ST(0)
DA /1 FIMUL m32int Multiply ST(0) by m32int and store result in ST(0)
DA /2 FICOM m32int Compare ST(0) with m32int
DA /3 FICOMP m32int Compare ST(0) with m32int and pop stack register
DA /4 FISUB m32int Subtract m32int from ST(0) and store result in ST(0)
DA /5 FISUBR m32int Subtract ST(0) from m32int and store result in ST(0)
DA /6 FIDIV m32int Divide ST(0) by m32int and store result in ST(0)
DA /7 FIDIVR m32int Divide m32int by ST(0) and store result in ST(0)
DA C0+i FCMOVB ST(0), ST(i) Move if below (CF=1)
DA C8+i FCMOVE ST(0), ST(i) Move if equal (ZF=1)
DA D0+i FCMOVBE ST(0), ST(i) Move if below or equal (CF=1 or ZF=1)
DA D8+i FCMOVU ST(0), ST(i) Move if unordered (PF=1)
DA E9 FUCOMPP Compare ST(0) with ST(1) and pop register stack twice
DB /0 FILD m32int Push m32int onto the FPU register stack.
DB /2 FIST m32int Store ST(0) in m32int
DB /3 FISTP m32int Store ST(0) in m32int and pop register stack
DB /5 FLD m80fp Push m80fp onto the FPU register stack.
DB /7 FSTP m80fp Copy ST(0) to m80fp and pop register stack
DB C0+i FCMOVNB ST(0), ST(i) Move if not below (CF=0)
DB C8+i FCMOVNE ST(0), ST(i) Move if not equal (ZF=0)
DB D0+i FCMOVNBE ST(0), ST(i) Move if not below or equal (CF=0 and ZF=0)
DB D8+i FCMOVNU ST(0), ST(i) Move if not unordered (PF=0)
DB E2 FNCLEX Clear floating-point exception flags without checking for pending unmasked floating-point exceptions.
DB E3 FNINIT Initialize FPU without checking for pending unmasked floating-point exceptions.
DB E8+i FUCOMI ST, ST(i) Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly
DB F0+i FCOMI ST, ST(i) Compare ST(0) with ST(i) and set status flags accordingly
DC /0 FADD m64fp Add m64fp to ST(0) and store result in ST(0)
DC /1 FMUL m64fp Multiply ST(0) by m64fp and store result in ST(0)
DC /2 FCOM m64fp Compare ST(0) with m64fp.
DC /3 FCOMP m64fp Compare ST(0) with m64fp and pop register stack.
DC /4 FSUB m64fp Subtract m64fp from ST(0) and store result in ST(0)
DC /5 FSUBR m64fp Subtract ST(0) from m64fp and store result in ST(0)
DC /6 FDIV m64fp Divide ST(0) by m64fp and store result in ST(0)
DC /7 FDIVR m64fp Divide m64fp by ST(0) and store result in ST(0)
DC C0+i FADD ST(i), ST(0) Add ST(i) to ST(0) and store result in ST(i)
DC C8+i FMUL ST(i), ST(0) Multiply ST(i) by ST(0) and store result in ST(i)
DC E0+i FSUBR ST(i), ST(0) Subtract ST(i) from ST(0) and store result in ST(i)
DC E8+i FSUB ST(i), ST(0) Subtract ST(0) from ST(i) and store result in ST(i)
DC F0+i FDIVR ST(i), ST(0) Divide ST(0) by ST(i) and store result in ST(i)
DC F8+i FDIV ST(i), ST(0) Divide ST(i) by ST(0) and store result in ST(i)
DD /0 FLD m64fp Push m64fp onto the FPU register stack.
DD /2 FST m64fp Copy ST(0) to m64fp
DD /3 FSTP m64fp Copy ST(0) to m64fp and pop register stack
DD /4 FRSTOR m94/108byte Load FPU state from m94byte or m108byte.
DD /6 FNSAVE m94/108byte Store FPU environment to m94byte or m108byte without checking for pending unmasked floating-point exceptions. Then re-initialize the FPU.
DD /7 FNSTSW m2byte Store FPU status word at m2byte without checking for pending unmasked floating-point exceptions.
DD C0+i FFREE ST(i) Sets tag for ST(i) to empty
DD D0+i FST ST(i) Copy ST(0) to ST(i)
DD D8+i FSTP ST(i) Copy ST(0) to ST(i) and pop register stack
DD E0+i FUCOM ST(i) Compare ST(0) with ST(i)
DD E1 FUCOM Compare ST(0) with ST(1)
DD E8+i FUCOMP ST(i) Compare ST(0) with ST(i) and pop register stack
DD E9 FUCOMP Compare ST(0) with ST(1) and pop register stack
DE /0 FIADD m16int Add m16int to ST(0) and store result in ST(0)
DE /1 FIMUL m16int Multiply ST(0) by m16int and store result in ST(0)
DE /2 FICOM m16int Compare ST(0) with m16int
DE /3 FICOMP m16int Compare ST(0) with m16int and pop stack register
DE /4 FISUB m16int Subtract m16int from ST(0) and store result in ST(0)
DE /5 FISUBR m16int Subtract ST(0) from m16int and store result in ST(0)
DE /6 FIDIV m16int Divide ST(0) by m64int and store result in ST(0)
DE /7 FIDIVR m16int Divide m64int by ST(0) and store result in ST(0)
DE C0+i FADDP ST(i), ST(0) Add ST(0) to ST(i), store result in ST(i), and pop the register stack
DE C1 FADDP Add ST(0) to ST(1), store result in ST(1), and pop the register stack
DE C8+i FMULP ST(i), ST(0) Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack
DE C9 FMULP Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack
DE D9 FCOMPP Compare ST(0) with ST(1) and pop register stack twice.
DE E0+i FSUBRP ST(i), ST(0) Subtract ST(i) from ST(0), store result in ST(i), and pop register stack
DE E1 FSUBRP Subtract ST(1) from ST(0), store result in ST(1), and pop register stack
DE E8+i FSUBP ST(i), ST(0) Subtract ST(0) from ST(i), store result in ST(i), and pop register stack
DE E9 FSUBP Subtract ST(0) from ST(1), store result in ST(1), and pop register stack
DE F0+i FDIVRP ST(i), ST(0) Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
DE F1 FDIVRP Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
DE F8+i FDIVP ST(i), ST(0) Divide ST(i) by ST(0), store result in ST(i), and pop the register stack
DE F9 FDIVP Divide ST(1) by ST(0), store result in ST(1), and pop the register stack
DF /0 FILD m16int Push m16int onto the FPU register stack.
DF /2 FIST m16int Store ST(0) in m16int
DF /3 FISTP m16int Store ST(0) in m16int and pop register stack
DF /4 FBLD m80 dec Convert BCD value to real and push onto the FPU stack.
DF /5 FILD m64int Push m64int onto the FPU register stack.
DF /6 FBSTP m80bcd Store ST(0) in m80bcd and pop ST(0).
DF /7 FISTP m64int Store ST(0) in m64int and pop register stack
DF E0 FNSTSW AX Store FPU status word in AX register without checking for pending unmasked floating-point exceptions.
DF E8+i FUCOMIP ST, ST(i) Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack
DF F0+i FCOMIP ST, ST(i) Compare ST(0) with ST(i), set status flags accordingly, and pop register stack
E0 cb LOOPNE rel8 Decrement count; jump short if count │ 0 and ZF=0
E0 cb LOOPNZ rel8 Decrement count; jump short if count │ 0 and ZF=0
E1 cb LOOPE rel8 Decrement count; jump short if count │ 0 and ZF=1
E1 cb LOOPZ rel8 Decrement count; jump short if count │ 0 and ZF=1
E2 cb LOOP rel8 Decrement count; jump short if count │ 0
E3 cb JCXZ rel8 Jump short if CX register is 0
E3 cb JECXZ rel8 Jump short if ECX register is 0
E4 ib IN AL, imm8 Input byte from imm8 I/O port address into AL
E5 ib IN AX, imm8 Input byte from imm8 I/O port address into AX
E5 ib IN EAX, imm8 Input byte from imm8 I/O port address into EAX
E6 ib OUT imm8, AL Output byte in AL to I/O port address imm8
E7 ib OUT imm8, AX Output word in AX to I/O port address imm8
E7 ib OUT imm8, EAX Output doubleword in EAX to I/O port address imm8
E8 cw CALL rel16 Call near, relative, displacement relative to next instruction
E8 cd CALL rel32 Call near, relative, displacement relative to next instruction
E9 cw JMP rel16 Jump near, relative, displacement relative to next instruction
E9 cd JMP rel32 Jump near, relative, displacement relative to next instruction
EA cd JMP ptr16:16 Jump far, absolute, address given in operand
EA cp JMP ptr16:32 Jump far, absolute, address given in operand
EB cb JMP rel8 Jump short, relative, displacement relative to next instruction
EC IN AL,DX Input byte from I/O port in DX into AL
ED IN AX,DX Input word from I/O port in DX into AX
ED IN EAX,DX Input doubleword from I/O port in DX into EAX
EE OUT DX, AL Output byte in AL to I/O port address in DX
EF OUT DX, AX Output word in AX to I/O port address in DX
EF OUT DX, EAX Output doubleword in EAX to I/O port address in DX
F0 LOCK Asserts LOCK# signal for duration of the accompanying instruction
F2 0F 10 /r MOVSD xmm1, xmm2/m64 Move scalar double-precision floating-point value from xmm2/m64 to xmm1 register.
F2 0F 11 /r MOVSD xmm2/m64, xmm Move scalar double-precision floating-point value from xmm1 register to xmm2/m64.
F2 0F 2A /r CVTSI2SD xmm, r/m32 Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm.
F2 0F 2C /r CVTTSD2SI r32, xmm/m64 Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer in r32 using truncation.
F2 0F 2D /r CVTSD2SI r32, xmm/m64 Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer r32.
F2 0F 51 /r SQRTSD xmm1, xmm2/m64 Computes square root of the low double-precision floating-point value in xmm2/m64 and stores the results in xmm1.
F2 0F 58 /r ADDSD xmm1, xmm2/m64 Add the low double-precision floating-point value from xmm2/m64 to xmm1.
F2 0F 59 /r MULSD xmm1, xmm2/m64 Multiply the low double-precision floating-point value in xmm2/mem64 by low double-precision floating-point value in xmm1.
F2 0F 5A /r CVTSD2SS xmm1, xmm2/m64 Convert one double-precision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1.
F2 0F 5C /r SUBSD xmm1, xmm2/m64 Subtracts the low double-precision floating-point values in xmm2/mem64 from xmm1.
F2 0F 5D /r MINSD xmm1, xmm2/m64 Return the minimum scalar double-precision floating-point value between xmm2/mem64 and xmm1.
F2 0F 5E /r DIVSD xmm1, xmm2/m64 Divide low double-precision floating-point value n xmm1 by low double-precision floating-point value in xmm2/mem64.
F2 0F 5F /r MAXSD xmm1, xmm2/m64 Return the maximum scalar double-precision floating-point value between xmm2/mem64 and xmm1.
F2 0F 70 /r ib PSHUFLW xmm1, xmm2/m128, imm8 Shuffle the low words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.
F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, imm8 Compare low double-precision floating-point value in xmm2/m64 and xmm1 using imm8 as comparison predicate.
F2 0F D6 MOVDQ2Q mm, xmm Move low quadword from xmm to MMX technology register.
F2 0F E6 CVTPD2DQ xmm1, xmm2/m128 Convert two packed double-precision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1.
F2 A6 REPNE CMPS m8,m8 Find matching bytes in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m16,m16 Find matching words in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m32,m32 Find matching doublewords in ES:[(E)DI] and DS:[(E)SI]
F2 AE REPNE SCAS m8 Find AL, starting at ES:[(E)DI]
F2 AF REPNE SCAS m16 Find AX, starting at ES:[(E)DI]
F2 AF REPNE SCAS m32 Find EAX, starting at ES:[(E)DI]
F3 0F 10 /r MOVSS xmm1, xmm2/m32 Move scalar single-precision floating-point value from xmm2/m64 to xmm1 register.
F3 0F 11 /r MOVSS xmm2/m32, xmm Move scalar single-precision floating-point value from xmm1 register to xmm2/m64.
F3 0F 2A /r CVTSI2SS xmm, r/m32 Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm.
F3 0F 2C /r CVTTSS2SI r32, xmm/m32 Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32 using truncation.
F3 0F 2D /r CVTSS2SI r32, xmm/m32 Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32.
F3 0F 51 /r SQRTSS xmm1, xmm2/m32 Computes square root of the low single-precision floating-point value in xmm2/m32 and stores the results in xmm1.
F3 0F 52 /r RSQRTSS xmm1, xmm2/m32 Computes the approximate reciprocal of the square root of the low single-precision floating-point value in xmm2/m32 and stores the results in xmm1.
F3 0F 53 /r RCPSS xmm1, xmm2/m32 Computes the approximate reciprocal of the scalar single-precision floating-point value in xmm2/m32 and stores the result in xmm1.
F3 0F 58 /r ADDSS xmm1, xmm2/m32 Add the low single-precision floating-point value from xmm2/m32 to xmm1.
F3 0F 59 /r MULSS xmm1, xmm2/m32 Multiply the low single-precision floating-point value in xmm2/mem by the low single-precision floating-point value in xmm1.
F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32 Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1.
F3 0F 5B /r CVTTPS2DQ xmm1, xmm2/m128 Convert four single-precision floating-point values from xmm2/m128 to four signed doubleword integers in xmm1 using truncation.
F3 0F 5C /r SUBSS xmm1, xmm2/m32 Subtract the lower single-precision floating-point values in xmm2/m32 from xmm1.
F3 0F 5D /r MINSS xmm1, xmm2/m32 Return the minimum scalar single-precision floating-point value between xmm2/mem32 and xmm1.
F3 0F 5E /r DIVSS xmm1, xmm2/m32 Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32
F3 0F 5F /r MAXSS xmm1, xmm2/m32 Return the maximum scalar single-precision floating-point value between xmm2/mem32 and xmm1.
F3 0F 6F /r MOVDQU xmm1, xmm2/m128 Move unaligned double quadword from xmm2/m128 to xmm1.
F3 0F 70 /r ib PSHUFHW xmm1, xmm2/m128, imm8 Shuffle the high words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.
F3 0F 7E MOVQ xmm1, xmm2/m64 Move quadword from xmm2/mem64 to xmm1.
F3 0F 7F /r MOVDQU xmm2/m128, xmm1 Move unaligned double quadword from xmm1 to xmm2/m128.
F3 0F C2 /r ib CMPSS xmm1, xmm2/m32, imm8 Compare low single-precision floating-point value in xmm2/m32 and xmm1 using imm8 as comparison predicate.
F3 0F D6 MOVQ2DQ xmm, mm Move quadword from mmx to low quadword of xmm.
F3 0F E6 CVTDQ2PD xmm1, xmm2/m64 Convert two packed signed doubleword integers from xmm2/m128 to two packed double-precision floating-point values in xmm1.
F3 6C REP INS r/m8, DX Input (E)CX bytes from port DX into ES:[(E)DI]
F3 6D REP INS r/m16,DX Input (E)CX words from port DX into ES:[(E)DI]
F3 6D REP INS r/m32,DX Input (E)CX doublewords from port DX into ES:[(E)DI]
F3 6E REP OUTS DX, r/m8 Output (E)CX bytes from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m16 Output (E)CX words from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m32 Output (E)CX doublewords from DS:[(E)SI] to port DX
F3 90 PAUSE Gives hint to processor that improves performance of spin-wait loops.
F3 A4 REP MOVS m8,m8 Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m16,m16 Move (E)CX words from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m32,m32 Move (E)CX doublewords from DS:[(E)SI] to ES:[(E)DI]
F3 A6 REPE CMPS m8,m8 Find nonmatching bytes in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m16,m16 Find nonmatching words in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m32,m32 Find nonmatching doublewords in ES:[(E)DI] and DS:[(E)SI]
F3 AA REP STOS m8 Fill (E)CX bytes at ES:[(E)DI] with AL
F3 AB REP STOS m16 Fill (E)CX words at ES:[(E)DI] with AX
F3 AB REP STOS m32 Fill (E)CX doublewords at ES:[(E)DI] with EAX
F3 AC REP LODS AL Load (E)CX bytes from DS:[(E)SI] to AL
F3 AD REP LODS AX Load (E)CX words from DS:[(E)SI] to AX
F3 AD REP LODS EAX Load (E)CX doublewords from DS:[(E)SI] to EAX
F3 AE REPE SCAS m8 Find non-AL byte starting at ES:[(E)DI]
F3 AF REPE SCAS m16 Find non-AX word starting at ES:[(E)DI]
F3 AF REPE SCAS m32 Find non-EAX doubleword starting at ES:[(E)DI]
F4 HLT Halt
F5 CMC Complement carry flag (CF)
F6 /0 ib TEST r/m8,imm8 AND imm8 with r/m8; set SF, ZF, PF according to result
F6 /2 NOT r/m8 Reverse each bit of r/m8
F6 /3 NEG r/m8 Two's complement negate r/m8
F6 /4 MUL r/m8 Unsigned multiply (AX <- AL * r/m8)
F6 /5 IMUL r/m8 AX <- AL * r/m byte
F6 /6 DIV r/m8 Unsigned divide AX by r/m8; AL <- Quotient, AH <- Remainder
F6 /7 IDIV r/m8 Signed divide AX by r/m8, with result stored in AL <- Quotient, AH <- Remainder
F7 /0 iw TEST r/m16,imm16 AND imm16 with r/m16; set SF, ZF, PF according to result
F7 /0 id TEST r/m32,imm32 AND imm32 with r/m32; set SF, ZF, PF according to result
F7 /2 NOT r/m16 Reverse each bit of r/m16
F7 /2 NOT r/m32 Reverse each bit of r/m32
F7 /3 NEG r/m16 Two's complement negate r/m16
F7 /3 NEG r/m32 Two's complement negate r/m32
F7 /4 MUL r/m16 Unsigned multiply (DX:AX <- AX * r/m16)
F7 /4 MUL r/m32 Unsigned multiply (EDX:EAX <- EAX * r/m32)
F7 /5 IMUL r/m16 DX:AX <- AX * r/m word
F7 /5 IMUL r/m32 EDX:EAX <- EAX * r/m doubleword
F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16; AX <- Quotient, DX <- Remainder
F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32 doubleword; EAX <- Quotient, EDX <- Remainder
F7 /7 IDIV r/m16 Signed divide DX:AX by r/m16, with result stored in AX <- Quotient, DX <- Remainder
F7 /7 IDIV r/m32 Signed divide EDX:EAX by r/m32, with result stored in EAX <- Quotient, EDX <- Remainder
F8 CLC Clear CF flag
F9 STC Set CF flag
FA CLI Clear interrupt flag; interrupts disabled when interrupt flag cleared
FB STI Set interrupt flag; external, maskable interrupts enabled at the end of the next instruction
FC CLD Clear DF flag
FD STD Set DF flag
FE /0 INC r/m8 Increment r/m byte by 1
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /0 INC r/m16 Increment r/m word by 1
FF /0 INC r/m32 Increment r/m doubleword by 1
FF /1 DEC r/m16 Decrement r/m16 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
FF /2 CALL r/m16 Call near, absolute indirect, address given in r/m16
FF /2 CALL r/m32 Call near, absolute indirect, address given in r/m32
FF /3 CALL m16:16 Call far, absolute indirect, address given in m16:16
FF /3 CALL m16:32 Call far, absolute indirect, address given in m16:32
FF /4 JMP r/m16 Jump near, absolute indirect, address given in r/m16
FF /4 JMP r/m32 Jump near, absolute indirect, address given in r/m32
FF /5 JMP m16:16 Jump far, absolute indirect, address given in m16:16
FF /5 JMP m16:32 Jump far, absolute indirect, address given in m16:32
FF /6 PUSH r/m16 Push r/m16
FF /6 PUSH r/m32 Push r/m32
